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Observer vonbk
Observer
7,838 Views
Registered: ‎11-21-2009

How to know where is block ram after place and route

Dear all,

 

I built a system including one CPU and boot memory.

I use block ram as boot memory. After synthesizing system,

I don't find the location information about this block ram. 

Do you know which file will keep information about the localtion

of this block ram ?

 

I don't use ISE ( ISE is so slow. I'm sorry to Xilinx when I said that :-) ),

I use xst and par ... command line  to synthesize this system. And I'd like

to use planahead tool to know about the distributed location of my system. 

But I don't know how to invoke planahead and show the distributed location

of my system.  ( I use ISE to synthesize one block ram, then I click planahead

I can see the distributed location of my system on Virtex4-LX80. That's

is my question purpose)

 

Purpose is: the cache size of CPU  is bigger (16KB IC + 16KB OC) so that it must

use more than 1 block ram ( exactly is 32 block rams), it'd better when these block rams are put

close together (I think so). So that after first trial synthesize I will re-synthesize

again I will put them with the RLOC constraint.

 

( Actually, I was not confident enough to put RLOC  constraint for boot memory and cache.

It's my first project with FPGA).

Please help me to correct my understanding or do you have any advice or tip.

Please feel free to teach me.

 

I don't find the file showing a resource location of Virtex4 LX80. If you know it

please tell me.

 

BRG,

Vonbk

 

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7 Replies
Xilinx Employee
Xilinx Employee
7,828 Views
Registered: ‎01-03-2008

Re: How to know where is block ram after place and route

You can open up the placed and routed NCD file using the FPGA Editor tool.  This will show all of the resources in the design and their locations including the Block RAM that you are looking for.
------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Observer vonbk
Observer
7,811 Views
Registered: ‎11-21-2009

Re: How to know where is block ram after place and route

Dear mcget,

 

Thank you so your help. I will try.

 

My system takes a lot of times to synthesis, place  and route. It takes more 

than 10hours on server 16GB.

 

I read devref manual, there is some informations to reduce the time:

1. First one is partition design. I did not use ISE, so how can I partition 

my design with xst command line.  It is really useful for me,I only modify

little to fixed some synthesis problem or improve our code, I must 

synthesis system again, it is quite waste my time to waiting all synthesis phase

finish, then read report and find out problem, and re-synthesis again. It is my current

nightmare.

 

I think that XST must support this scheme:

My system have a lot of modules, I will synthesis each module invidually then

we will put it together in top modules ( of course, there is some modules is sub 

module of other modules). I also read the xst manual, there is one black_box 

options and -sd in ngdbuild command, but as my understanding we must mark 

which module is black_box manually, is there any way to do it automatically.

(My system has one CPU IP core, it has so much modules, it was developed by

another group,I just take it and build FPGA environment for evaluation purpose)

 

2. Second is smartexplorer: we have lsf cluster, but I read the smartexplorer manual,

I think the manual is little bit hard for understanding. Do you know other reference 

to teach me how to famillar with this technology?

 

3. The synthesis report needs not meet my requirement:

3.1 It use a lot of resource: it consumes 93% slice resource on Virtex4-LX80.

Other usage resource such as block ram ...  usage are <30%

Do you have any advice about XST options to reduce slice usage: my 

current options is optimixation for area with this level option is 2 ( highest effort).

It is just first trial synthesis, we will put some IPs in this system. I wonder that 

if we can reduce the slice usage, we will do our plan in future ( My current system 

only has one CPU+FPU <-> interconnect <-> boot memory. It is so simple

now). We don't have budget and permission to purchase other higher resource 

device.

 

3.2 The XST report said that maximum frequency is ~45 MHz, it is quite slow than

my expectation. Do you advice for me  to improve our clock frequency?

( i also set register_balance otpions is yes)

So tha, there is a lot message complaint about timing violation.

 

I'm sorry I'm new FPGA user. ( This is my first project to deal with FPGA).

Noone in my team had the experience with FPGA before.

 

Happy Chirstmas.

 

BRG,

Vonbk

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Explorer
Explorer
7,798 Views
Registered: ‎01-04-2009

Re: How to know where is block ram after place and route


10 hours is a very long time , ISE should speed this up by a significant factor.
I have found using XPS to compile designs is a lot slower.
 
Even so...... 10 hours sounds like you have not correctly allocated your ram to ram resources, and possibly the design is trying to simulate the ram in discrete logic.
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Observer vonbk
Observer
7,790 Views
Registered: ‎11-21-2009

Re: How to know where is block ram after place and route

Dear code_slave,

 

I check the log file (just briefly ) and have some simple calculations, I also 

use FPGA_Editor, I'm sure that, boot_memory and cache were implemented

by block ram. Actually, I also insert synthesis contrainst to force

xst synthesizes boot_memory and cache as block ram.

 

I think that the ratio of slice is so high, I don't know which modules

consume almost sclie resource, I must re-check log file more carefully.

 

Do you know the fast way ( such as script or my trick way) to 

find the "hunter" module ?

 

I wonder about the tag,dirty ram ( I put the constraint for xst implements this 

tag and  dirty bit are "distributed" ram ), it may implement as slice logic.

 

Thank you so much your sugesstion, it may useful in my case.

 

BRG,

Vonbk

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Xilinx Employee
Xilinx Employee
7,784 Views
Registered: ‎11-28-2007

Re: How to know where is block ram after place and route

FWIW, just in case you want to get BRAM placements after the implementation is done (i.e. from NCD), you may want to give ADEPT (http://mysite.verizon.net/jimwu88/adept/) a try. It displays the BRAM instances and their locations. It can also export that to an Excel spreadsheet or UCF.

 

Below is a snapshot of ADEPT component view. Additional information can be found in this blog: http://myadeptblog.blogspot.com/2009/12/virtex5-component-view.html

 

Message Edited by jimwu on 12-26-2009 04:49 PM
Cheers,
Jim
comp_view2.gif
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Xilinx Employee
Xilinx Employee
7,731 Views
Registered: ‎11-28-2007

Re: How to know where is block ram after place and route

If you run MAP with "-detail" option, it will generate a detailed .mrp report with module level utilization. Or you can use ADEPT (http://mysite.verizon.net/jimwu88/adept/) to read the NCD and it will get the hierarchical logic utilization for you (see the snapshot below). Check http://myadeptblog.blogspot.com/2009/12/logic-utilization-view.html for additional details.

vonbk wrote: 
 

I think that the ratio of slice is so high, I don't know which modules

consume almost sclie resource, I must re-check log file more carefully.

 

Do you know the fast way ( such as script or my trick way) to 

find the "hunter" module ?

 

I wonder about the tag,dirty ram ( I put the constraint for xst implements this 

tag and  dirty bit are "distributed" ram ), it may implement as slice logic.

 

Vonbk

 

Cheers,
Jim
logic_util_view.gif
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Observer vonbk
Observer
7,714 Views
Registered: ‎11-21-2009

Re: How to know where is block ram after place and route

Dear jimwu,

 

Thank you so much for your help. I will try.

 

RG,

Vonbk

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