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Explorer
Explorer
10,478 Views
Registered: ‎03-06-2014

How to see Fast/Slow/High/Low corners in Static Timing Analysis in ISE?

Hello,

 

I am using ISE14.7 on a Virtex-5 (XC5VLX50T) target device.

 

I would like to do the best case and worst case analysis to find their corners with PVT variation. I refered to page 19 of UG625 (v. 13.2) July 6, 2011, about TEMPERATURE and VOLTAGE constraints. But I do not know whether the correct way to do that to find the best case and worst case timing delay analysis in Static Timing Analyzer?

 

Any kind help is cordially appreciated.

 

Regards,

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Xilinx Employee
Xilinx Employee
9,737 Views
Registered: ‎02-16-2014

Re: How to see Fast/Slow/High/Low corners in Static Timing Analysis in ISE?

Hi @msdarvishi

 

The older devices, Virtex-5 and Virtex-4 FPGA, had options to use the TEMPERATURE and VOLTAGE constraints in ISE tools and to change this value in Timing Analyzer for reporting.

You can also derate the temperature to analyze timing (by using speed files) for a specific temperature while running Timing Analysis. Check figure below.

Capture.JPG

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