How to see Fast/Slow/High/Low corners in Static Timing Analysis in ISE?
I am using ISE14.7 on a Virtex-5 (XC5VLX50T) target device.
I would like to do the best case and worst case analysis to find their corners with PVT variation. I refered to page 19 of UG625 (v. 13.2) July 6, 2011, about TEMPERATURE and VOLTAGE constraints. But I do not know whether the correct way to do that to find the best case and worst case timing delay analysis in Static Timing Analyzer?