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Visitor renfulin
Visitor
1,531 Views
Registered: ‎04-06-2010

How to sovle the MIG problems on ML523 board with XC5VLX110T-1136?

The version of the software is MIG2.1, ISE10.1.01. FPGA is XC5VLX110T-1136, speed -1.

 

I generated a DDR2 memory controller core with MIG2.1.  

Firstly, the "ddr2_sdram.ucf" is updated according to the DDR2 pin settings in ML523 User Guide. All of the pin locations are modified.

Secondly, I use Verify UCF function in MIG2.1 to verify the updated UCF file and then copy the LOC contraints generated by MIG2.1 into the UCF file. And the top level Verilog file of ddr2_sdram.v also is updated.

Thirdly, fix the DCI problems encounterd in map procedure. Add DCI_CASCADE into UCF file.

 

However, after the above opeations, the map procedure still can't be finished successfully.

 

The error is

Place:840 - IO Clock Net
   "u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs[6]" cannot possibly
   be routed to component "u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/dq_ce[6]"
   (placed in clock region "CLOCKREGION_X0Y2"), since it is too far away from
   source BUFIO
   "u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_bufio_dqs"
   (placed in clock region "CLOCKREGION_X0Y6"). The situation may be caused by
   user constraints, or the complexity of the design. Constraining the
   components related to the regional clock properly may guide the tool to find
   a solution.

 

To sovle the problems, I replaced the BUFIO with BUFG in phy_dqs_iob.v. Then PAR can be finished with timing errors. There were about 20 setup timing errors. From the timing anlaysis report, the net route delay is about 3.5ns which is biger than the requirement of DQS.  

 

Anyone please tell me how to solve the problems. Thanks very much!!!

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