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Visitor kevintruong
Visitor
42,106 Views
Registered: ‎03-07-2010

How to use IBUFDS , OBUFDS (differential signals buffers) for Virtex-5 in Verilog

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Hello,

 

I'm using Virtex 5 with some High-speed Differential Signals for both INPUTS and OUTPUTS. I know that I have to use the buffers for this but I'm not quite sure how to code it in Verilog. Thus I have two questions regarding this:

 

1. Where do I instantiate IBUFDS and OBUFDS? 

2.  Can I have them inside my top module as shown below?

3. What do the symbols "#" behind IBUFDS and OBUFDS mean? 

 

Thanks for helping.

 


module differential_signals_test_top (

input CLOCK_IN_P,

input CLOCK_IN_N,

input [15:0] DATA_IN_P,

input [15:0] DATA_IN_P,

//output CLOCK_OUT_P,

//output CLOCK_OUT_N,

output [15:0] DATA_IN_BUFF

)

 

reg CLOCK_IN;

reg CLOCK_OUT;

reg [15:0] DATA_IN;

reg [15:0] DATA_IN_BUFF;

 

IBUFDS #(

.CAPACITANCE("DONT_CARE"),

.DIFF_TERM("FALSE"),

.IBUF_DELAY_VALUE("0"),

.IFD_DELAY_VALUE("AUTO"),

.IOSTANDARD("DEFAULT")

) IBUFDS_inst (

.O(CLOCK_IN),

.I(CLOCK_IN_P),

.IB(CLOCK_IN_N)

);

 

OBUFDS #(

.IOSTANDARD("DEFAULT")

) OBUFDS_inst (

.O(CLOCK_OUT_P),

.OB(CLOCK_OUT_N),

.I(CLOCK_OUT)

);

 

IBUFDS #(

.CAPACITANCE("DONT_CARE"),

.DIFF_TERM("FALSE"),

.IBUF_DELAY_VALUE("0"),

.IFD_DELAY_VALUE("AUTO"),

.IOSTANDARD("DEFAULT")

) IBUFDS_inst (

.O(DATA_IN),

.I(DATA_IN_P),

.IB(DATA_IN_N)

);

 

// send out CLOCK_OUT

 

// latch DATA_IN toANOTHER BUFFER AT every CLOCK_IN

 

always @ (posedge CLOCK_IN)

begin

    DATA_IN_BUFF <= DATA_IN;

end

 

endmodule

 

Message Edited by kevintruong on 03-07-2010 12:50 AM
1 Solution

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Explorer
Explorer
58,768 Views
Registered: ‎02-27-2010

Re: How to use IBUFDS , OBUFDS (differential signals buffers) for Virtex-5 in Verilog

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Welcome to the brand new world of Verilog (or newer than the original version if you learned Verilog about a decade ago).  Since Verilog2001, the syntax "module_type #( -param_list- ) module_instance_name ( -port_list )" helps to shorten the typically very long list of defparam modifiers to a module.  The parameteres are used to "tune" aspects designed into the module.  The # is an identifier that tells the synthesizer and the reader that the following optional list is for parameters.

 

I usually instantiate my IOBUFs at the top level as well though I'm sure you could bury them deeper in your hierarchy if needed, you just need to carry the differential pair through the hierarchy.  Keeping the diffs in the top means only one signal needs to carry through rather than the pair.

 

What you may be missing in your code is the array of instances to bring in all 16 bits of the data.  Just change"IBUFDS_inst" to "IBUFDS_inst[15:0]" and you should get all 16 bits coming through.

5 Replies
Highlighted
Explorer
Explorer
58,769 Views
Registered: ‎02-27-2010

Re: How to use IBUFDS , OBUFDS (differential signals buffers) for Virtex-5 in Verilog

Jump to solution

Welcome to the brand new world of Verilog (or newer than the original version if you learned Verilog about a decade ago).  Since Verilog2001, the syntax "module_type #( -param_list- ) module_instance_name ( -port_list )" helps to shorten the typically very long list of defparam modifiers to a module.  The parameteres are used to "tune" aspects designed into the module.  The # is an identifier that tells the synthesizer and the reader that the following optional list is for parameters.

 

I usually instantiate my IOBUFs at the top level as well though I'm sure you could bury them deeper in your hierarchy if needed, you just need to carry the differential pair through the hierarchy.  Keeping the diffs in the top means only one signal needs to carry through rather than the pair.

 

What you may be missing in your code is the array of instances to bring in all 16 bits of the data.  Just change"IBUFDS_inst" to "IBUFDS_inst[15:0]" and you should get all 16 bits coming through.

Visitor kevintruong
Visitor
42,073 Views
Registered: ‎03-07-2010

Re: How to use IBUFDS , OBUFDS (differential signals buffers) for Virtex-5 in Verilog

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Thanks John :) 
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Visitor kevintruong
Visitor
41,852 Views
Registered: ‎03-07-2010

Re: How to use IBUFDS , OBUFDS (differential signals buffers) for Virtex-5 in Verilog

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Hi Jon,

 

Any idea with this error: "Connection to port 'O' of instance array 'IBUFDS_data_inst' must be a net lvalue

 

module differential_signals_test_top (

input CLOCK_IN_P,

input CLOCK_IN_N,

input [15:0] DATA_IN_P,

input [15:0] DATA_IN_P,

//output CLOCK_OUT_P,

//output CLOCK_OUT_N,

output [15:0] DATA_IN_BUFF

)

 

reg CLOCK_IN;

reg CLOCK_OUT;

reg [15:0] DATA_IN;

reg [15:0] DATA_IN_BUFF;

 

IBUFDS #(

.CAPACITANCE("DONT_CARE"),

.DIFF_TERM("FALSE"),

.IBUF_DELAY_VALUE("0"),

.IFD_DELAY_VALUE("AUTO"),

.IOSTANDARD("DEFAULT")

) IBUFDS_inst (

.O(CLOCK_IN),

.I(CLOCK_IN_P),

.IB(CLOCK_IN_N)

);

 

OBUFDS #(

.IOSTANDARD("DEFAULT")

) OBUFDS_inst (

.O(CLOCK_OUT_P),

.OB(CLOCK_OUT_N),

.I(CLOCK_OUT)

);

 

IBUFDS #(

.CAPACITANCE("DONT_CARE"),

.DIFF_TERM("FALSE"),

.IBUF_DELAY_VALUE("0"),

.IFD_DELAY_VALUE("AUTO"),

.IOSTANDARD("DEFAULT")

) IBUFDS_data_inst[15:0] (

.O(DATA_IN),

.I(DATA_IN_P),

.IB(DATA_IN_N)

);

 

// send out CLOCK_OUT

 

// latch DATA_IN toANOTHER BUFFER AT every CLOCK_IN

 

always @ (posedge CLOCK_IN)

begin

    DATA_IN_BUFF <= DATA_IN;

end

 

endmodule 

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Explorer
Explorer
41,849 Views
Registered: ‎02-27-2010

Re: How to use IBUFDS , OBUFDS (differential signals buffers) for Virtex-5 in Verilog

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Why are you declaring CLOCK_IN, CLOCK_OUT, aand DATA_IN as reg values?  It looks like only DATA_IN_BUFF needs to be a register, the others should be wires because they get continuous assignments through the ports.  (Also, you have two DATA_IN_P instances in your port list.)

 

A "reg" is not a "net lvalue" which is why the error.  The errors really are rather descriptive.

 

- John_H

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23,968 Views
Registered: ‎01-08-2016

Re: How to use IBUFDS , OBUFDS (differential signals buffers) for Virtex-5 in Verilog

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Thanks Guys..

 

IBUF instantiation works for me

 

 IBUFDS #(
.CAPACITANCE("DONT_CARE"),
.DIFF_TERM("FALSE"),
.IBUF_DELAY_VALUE("0"),
.IFD_DELAY_VALUE("AUTO"),
.IOSTANDARD("LVCMOS18")
) IBUFDS_inst (
.O(CNF_DONE_OT1_MFPGA_IBUF),
.I(CNF_DONE_OT1_MFPGA),
.IB()
);

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