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Explorer
Explorer
7,970 Views
Registered: ‎11-28-2011

I/O set to fixed level pre, during, post configuration

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What is a way I can guarantee the state of an FPGA output or input pre, during, and post configuration. Aside from having an external pull up, I want to ensure the state of the signal is always kept at a certain level and doesn't inadvertently be the opposite value.

 

What about using the HSWAPEN pin?

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Instructor
Instructor
13,711 Views
Registered: ‎08-14-2007

Re: I/O set to fixed level pre, during, post configuration

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HSWAPEN or PUDC_B depending on the FPGA family set the pullups on all I/O's during configuration.  You don't have the option to pull some high and others low.  There's another issue with relying on these pullups.  All IOB's are tristate for some period of time before confuration begins.  You cannot change this behavior.  So in essence if your output needs to be high from power-up until the FPGA is configured, an external pullup is necessary.  If you can afford to wait until initialization is complete (can be a few milliseconds depending on the part size) then HSWAPEN could help you.  If you need an output to always remain low, then a pull-down resistor is the only choice.  Some FPGA families have a few pins marked HDC or LDC which are actively driven high or low respectively during configuration.  However again it is my understanding that this active drive only starts after initialization (when INIT_B first goes high after power-up).

-- Gabor
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1 Reply
Instructor
Instructor
13,712 Views
Registered: ‎08-14-2007

Re: I/O set to fixed level pre, during, post configuration

Jump to solution

HSWAPEN or PUDC_B depending on the FPGA family set the pullups on all I/O's during configuration.  You don't have the option to pull some high and others low.  There's another issue with relying on these pullups.  All IOB's are tristate for some period of time before confuration begins.  You cannot change this behavior.  So in essence if your output needs to be high from power-up until the FPGA is configured, an external pullup is necessary.  If you can afford to wait until initialization is complete (can be a few milliseconds depending on the part size) then HSWAPEN could help you.  If you need an output to always remain low, then a pull-down resistor is the only choice.  Some FPGA families have a few pins marked HDC or LDC which are actively driven high or low respectively during configuration.  However again it is my understanding that this active drive only starts after initialization (when INIT_B first goes high after power-up).

-- Gabor
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