01-19-2012 02:41 AM
I am going to implentment two serial link protocol in one design.
I generate two ip core by wizard (ver 1.12)
It always faied when synthesis, the error message is
ERROR:HDLCompiler:687 - "/home/walter/g3/fpga/v6-mgt-trial/ipcore_dir/mgt_sata3/example_design/frame_gen.v" Line 69: Illegal redeclaration of module <FRAME_GEN>.
Is there any way to have different rate serial link in one design by GTX ?
01-19-2012 06:10 PM
01-13-2014 12:17 PM
I have the same problem when I try to use different speed configuration for each serdes,
is there any one know how to config the serdes to make sure each serdes be able to run at different speed or different protocol?
01-13-2014 12:30 PM
The original post is one year old. If you need different functions in a module then the module name must also be different.
01-20-2014 02:41 AM