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Newbie
Newbie
9,486 Views
Registered: ‎05-29-2014

IODELAY cascade in virtex6

Hello,

 

I am trying to cascade two IODELAY elements to create lager delay value. I instantiated one IDELAYCTRL and two IODELAYE1 and make two IODELAYE1  work in VAR_LOADABLE mode.(assume one delay 200ps, another delay 300ps).

1.I can't see the expected delay value(200ps + 300ps) in RTL simulation

2.But I can see the expected delay value(200ps + 300ps) in Post Rute simulation.

 

why the result different in this two simulation?

can I use two or more IODELAY elements in this manner? if yes, what should be take care?

 

Thanks!

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2 Replies
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Moderator
Moderator
9,475 Views
Registered: ‎01-16-2013

Hello @linjin ,

 

First of all IODELAY in cascade is not an recommanded practice.

Because there is no routing directly from one IODELAY to the other IODELAY. Although it's possible to connect both IODELAY in cascade but it uses fabric routing instead of dedicated routing.

There are issues if you will connect IODELAYS in cascade like jitter and non-expected delay behaviour.

 

Regarding simulation differance in RTL simulation and Post route simulation:

>> RTL simulation is just an functional simulation to jugde your design whether functionality is as expected or not?

>> You can refer RTL simulation and modify your code according to your requirement. In other words RTL Simulation is just a referance simulation.

 

>> Post-route simulation is the actuall simulation which include all component delay+routing delay.

>> Post-route simulation is the behavioural representation of your hardware. 

>>If post-route simulation meets your expectation then 99% of times it sure that it will work on hardware.

 

Hope above explanation will help.

 

Thanks,

Yash

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Moderator
Moderator
9,423 Views
Registered: ‎01-16-2013

Hello @linjin ,

 

If above information helps you please mark the answer as accepted solution. If you still have any doubt related to this post reply.

 

Thanks,

Yash

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