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Visitor
Visitor
5,449 Views
Registered: ‎10-04-2012

IOs distribution on ADC Interface design of XAPP 1071.

Hello,

I have a doubt about IOs distribution at  ADC interface design of XAPP 1071 (Connecting Virtex-6 FPGAs to ADCs withSerial LVDS Interfaces and DACs with Parallel LVDS Interfaces) on a Virtex-6.

 

IOs locked in different I/O banks can generate signficant routing delays for this kind of design? 


For example, can I lock BITCLOCK at bank X, FRAMECLOCK at bank Y and DATA in bank Z without lose the correct alignment?

 

Or this kind of care can be disregarded and the routing delay on different banks is negligible?

 

I searched for answers about IOs on differente banks  but i didn´t find anything. I´m believe that this can be disregarded but i´m asking to be sure.

 

Thanks!

Iliézer Tamagno

 

 

 

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Scholar
Scholar
5,437 Views
Registered: ‎02-27-2008

I,

 

Placement of IO's may affect timing adversely (in fact it often may make timing worse, or impossible to meet).

 

Best is to not constrain the IO's, and see where the tools want to place the IO's to meet the constraints.  Then use PlanAhead (PinAhead) to constrain the IO in an intelligent way to make layout easier AND also meet your timing.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Scholar
Scholar
5,436 Views
Registered: ‎02-27-2008

And,

 

The placement in the app note was tested and works.

 

Any changes, and you need to verify that it still works....

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Visitor
Visitor
5,429 Views
Registered: ‎10-04-2012

Thanks Austin

I will follow your instructions wherever I can. But for my design now, I´m using ML605 development kit to create the prototype, and just some Virtex-6 IOs are available at FMC connectors. So, I need to constraint some IOs but I I can´t constraint all IOs of the ADC interface at the same bank, I will have to split this signals in two different banks. I just want to know if there some relationship between the banks and routing, or if there is no relationship and the only option I have is testing.


ADC interface is:

  • 1 LVDS BitClock
  • 1 LVDS FrameClock
  • 8 LVDS Data

Now, BitClock and Data from 1 to 6 are in bank 23 and FrameClock and Data 7 to 8 are in bank 14. I can´t join this signals at the same bank because I have 4 ADC interfaces and there isn´t a way to split all the 4 ADC Interfaces signals each in one bank.  I will have to split, at least, one ADC interface. 

 

If you have some suggestion about how divide this signals I´ll apreciate.

 

Thanks!

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