02-02-2010 07:28 AM - edited 02-02-2010 07:33 AM
I am using an evualuation board with a Virtex 2 pro on it. My I/O are connected to banks powered with 2.5V.
Is there a risk to damage the FPGA if I connect an LVTT Lsignal at 3.3V on this connector?
Thank you for answers.
02-02-2010 09:58 AM
Yes. You need to not exceed the abs max specifications in the data sheet.
Often "LVTTL" means CMOS< and the 3.3v drivers pull strongly to 3.3v, forward biasing the clamp diodes, causing the Vcco of the bank to be powered from the IOs, and not from the power supply (power supplies do not sink current, so Vcco goes up to ~2.8 volts.
It is suggested to put a 100 ohm resistor in series from the 3.3v output, to the 2.5v input placed at the 2.5v input.
If you have the IBIS models of the driver (and download the Xilinx IBIS models), you may simulate what happens, and you may not need a resistor if the outputs do not pull to 3.3v.
02-02-2010 11:10 PM
Do you think that I have to put that resistance if on the other side the 3.3V LVTTL signal (driver) is delivered from a spartan 3?
02-03-2010 07:21 AM
As long as the resistor is close to either the driver, or the receiver, you should be fine.
By placing it at the driver, you drive the 50 ohm link between the two weakly, which means that you absorb any returning reflections (good).
Better is at the receiver, as the receiver already has a very high input impedance, so the resistor does not affect the signal integrity much at all.
Again, if you simulate the driver, and the receiver, using an IBIS simulator, you would see what I mean.
If you do not have access to these tools, consider getting it, as one pcb redesign costs more than the tools (the tools pay for themselves with one mistake you could have avoided).
What is the driver part number? I could run my tools, and post back what I see,
04-21-2010 09:28 PM
I am also facing a similar situation on a board with Virtex 5 FGPA. I am forced to connect a LVCMOS_3.3V O/P of an on-board ADC to the FPGA I/O bank powered by 2.5V. As suggested by you, I connected a 100 ohm resistor close to the receiver and simulated the connection using HyperLynx. I am attaching the waveform observed at the receiver with and without a 100 ohm resistor (Figure-1 and Figure-2 respectively). I will appreciate if you could comment on the results and advice about the safety of this connection.
04-22-2010 09:30 AM
I am also facing a similar situation on a board with Virtex 5 FGPA. I am forced to connect a LVCMOS_3.3V O/P of an on-board ADC to the FPGA I/O bank powered by 2.5V
This is why you try to do as much FPGA design BEFORE approviing the PCB artwork for fab.
04-26-2010 09:09 PM
I have one more related doubt. VIH_max specified in the Virtex-5 datasheet for LVCMOS25 is VCCO+0.3 =2.8 V. VIH in the simulation results is close to 3 V with and without the resistor. Can I still go ahead with the connection or shall I use a level converter?
04-27-2010 07:57 AM
The Vih is not an issue. The 100 ohms is recommened in numerous applications notes, and technical answers.
The only issue, is that you should check that the Vcco stays at 2.5 volts: if too many IOs are being pulled to 3.3v through 100 ohm resistors, you may need to add a resistor to ground on the 2.5v Vcco to keep the Vcco at 2.5 volts (also in the applications notes, and answers).