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Visitor
Visitor
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Registered: ‎09-13-2012

LVDS Sigals connect to A Bank with +3.3V Vcco

Can I Connect a pair of Differential signals to a bank with +3.3V Vcco supply in v5sx95t? The Differential Signals are input to v5sx95t GC pins in bank 4.

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Scholar
Scholar
10,784 Views
Registered: ‎02-27-2008

LVDS is a standard.

 

The Vcco voltage may be 2.5, or 3.3, or whatever:  it does not matter (as long as the interface is LVDS standard).

 

OK?

Austin Lesea
Principal Engineer
Xilinx San Jose
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Professor
Professor
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Registered: ‎08-14-2007


@austin wrote:

LVDS is a standard.

 

The Vcco voltage may be 2.5, or 3.3, or whatever:  it does not matter (as long as the interface is LVDS standard).

 

OK?


That's part of the story.  For Virtex 5, only LVDS25 (Vcco = 2.5V) offers you the choice of using the

DIFF_TERM built-in termination.

 

-- Gabor

-- Gabor
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Scholar
Scholar
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Registered: ‎02-27-2008

Good point:  the V5 is specified to use 2.5 v on Vcco for LVDS,

 

If you use 3.3v, the diff_term is stronger (about 80 ohms), and not 100 ohms.  Everything else works just fine,

 

That said, if you simulate the signal integrity with the lowered impedance, and if it looks fine, then it will work fine.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Professor
Professor
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Registered: ‎08-14-2007


@austin wrote:

Good point:  the V5 is specified to use 2.5 v on Vcco for LVDS,

 

If you use 3.3v, the diff_term is stronger (about 80 ohms), and not 100 ohms.  Everything else works just fine,

 

That said, if you simulate the signal integrity with the lowered impedance, and if it looks fine, then it will work fine.

 

 


I've actually done this, but the tools don't really support it.  I had to tell ISE that the bank was powered

with 2.5V to get the DIFF_TERM.  Otherwise you'll get an error when you map the design.  If you have

other IO standards in that bank, they also will have different characteristics if you report the wrong

Vcco voltage.  So this is possible but you need to understand the ramifications.  For example if you

also have LVCMOS outputs on the same bank, and use the LVCMOS25 standard even though the

voltage is 3.3V, your output drive will be stronger than what you selected - possibly causing signal

integrity problems.  If you reduce the drive strength, the tools will mis-report the clock to output

timing, etc.

 

I have to say that the only reason I have done this is that a board was designed before I found out

about the 2.5V Vcco requirement for DIFF_TERM and the board had no provision for external

termination.  I would not recommend it for a new design.

 

-- Gabor

-- Gabor
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Scholar
Scholar
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Registered: ‎02-27-2008

Agree,

 

It is a poor solution to a problem:  better to just do it right the first time.


But, if they do not need internal termination, or if they can terminate externally (this is a clock signal, they often work just fine with no termination at all!) then it is OK, except for the need to ignore the error that a 2.5v lvds io is in a 3.3 v bank.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Instructor
Instructor
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Registered: ‎07-21-2009

Telling ISE that VCCO is 2.5V when it is in fact 3.3V may work as an expedient workaround, as Gabor describes.  On the other hand, it will absolutely fail if the design includes LVCMOS33 outputs on the same IO bank, as this requires 3.3V VCCO.

 

The two VCCO requirements -- 3.3V for LVCMOS33 output and 2.5V for LVDS_25 differential termination in a single IO bank -- are in direct conflict with one another.

 

-- Bob Elkind

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Explorer
Explorer
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Registered: ‎11-28-2011

I assume the same for VCCO of 1.8V.  Would LVDS work with VCCO of 1.8V? Would ISE14.x DIFF_TERM support 1.8V? If not, then would external pull ups have to be used?

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Scholar
Scholar
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Registered: ‎02-27-2008

p,

 

What device?  The original post was regarding a Virtex 5 part.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Explorer
Explorer
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Registered: ‎11-28-2011

V5 LX50.  The thought is the possiblity of not having to use a 2.5v regulator.  

 

We currently receive and transmit LVDS signals, however one set is LVDS_EXT25

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Scholar
Scholar
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Registered: ‎02-27-2008

p,

 

V5 LVDS requires a 2.5V supply to operate properly.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Explorer
Explorer
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Registered: ‎11-28-2011

Austin,

what about the other side of the link, which is a ZC7045. Can that run LVDS with 1.8V?

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Scholar
Scholar
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Registered: ‎02-27-2008

p,

 

Yes, at 28nm, the Vcco is 1.8v for LVDS, so yes, LVDS from a 1.8v Vcco bank in Zynq may be connected to a Virtex 5 LVDS bank at a Vcco of 2.5 volts.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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