I want to test my DAC ASIC using Virtex-6 FPGA and the ML605 Evaluation board. The test setup (see attached .png file), as suggested in application note XAPP1071, requires me to send out a clock from DAC. But since I am using only LVDS receivers and DAC on my ASIC, I do not want to build transmitter for transmitting clock from my DAC.
I want to give clock from Virtex-6 back to it in LVDS form. In other words, I want to generate a clock of desired frequency on the FPGA itself and route it back to the FPGA, considering it as clock output from my DAC.
1) Can anyone suggest how I can generate clock and feed it back?
2) Do I have any control on the clock frequency as well?