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Contributor
Contributor
9,041 Views
Registered: ‎07-24-2012

MIG 3.6 DDR2 design doesn't meet all timing constraints

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Greetings!

 

I generated a DDR2 memory code using MIG for Virtex-5. I followed the flow in the user guide to create a project in EDK XPS. When I try to generate the bit steam it fails with

 

PAR could not meet all timing constraints.

 

I did verify my system.ucf again using MIG but the error doesn't go away. I can sucessfully build the bit file using example_design and user_design in ISE but I cannot get it to work in XPS.

 

I am suspecting that the differential clocking scheme is causing the problems. I am attaching MHS, UCF, and the timing report.

 

 

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Contributor
Contributor
11,867 Views
Registered: ‎07-24-2012

Re: MIG 3.6 DDR2 design doesn't meet all timing constraints

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I have just updated from 12.3 to 13.4 and everything passed!

The only thing I had to change was  clock_generator version

 

Now I am using  PARAMETER HW_VER = 4.03.a instead of 4.00

 

 

 

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Contributor
Contributor
9,038 Views
Registered: ‎07-24-2012

Re: MIG 3.6 DDR2 design doesn't meet all timing constraints

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Here is the UCF and the timing report is attached

 

Net fpga_0_rst_1_sys_rst_pin TIG;
Net fpga_0_rst_1_sys_rst_pin IOSTANDARD=LVCMOS18;
Net fpga_0_rst_1_sys_rst_pin LOC=AD34;

Net xtal_clk_p LOC = AG15;
Net xtal_clk_p IOSTANDARD=LVDS_25;
Net xtal_clk_p DIFF_TERM = TRUE; # DCI?

Net xtal_clk_n LOC = AH15;
Net xtal_clk_n IOSTANDARD=LVDS_25;
Net xtal_clk_n DIFF_TERM = TRUE;

## xtal level constraints
#Net "xtal_clk_p" TNM_NET = xtal_clk_p;
#TIMESPEC TS_xtal_clk_p = PERIOD xtal_clk_p 10 ns HIGH 50 %;
#Net xtal_clk_n TNM_NET = xtal_clk_n;
#TIMESPEC TS_xtal_clk_n = PERIOD xtal_clk_n 3.750 ns HIGH 50 %;

## UART
Net fpga_0_RS232_sout_pin LOC=AH24  |  IOSTANDARD=LVCMOS33;
Net fpga_0_RS232_sin_pin LOC=AK22  |  IOSTANDARD=LVCMOS33;
Net fpga_0_RS232_ctsN_pin LOC=F8;
Net fpga_0_RS232_rtsN_pin LOC=F9;


############################################################################
# Clock constraints                                                        #
############################################################################

#NET "u_ddr2_infrastructure/sys_clk_ibufg" TNM_NET =  "SYS_CLK";
#TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK" 3.75 ns HIGH 50 %;


#NET "fpga_clk100" TNM_NET = "CLK";
#TIMESPEC "TS_CLK" = PERIOD "CLK" 10.0 ns HIGH 50%;
#OFFSET = OUT AFTER "fpga_clk100" REFERENCE_PIN "mc_clk" RISING;
#OFFSET = OUT AFTER "fpga_clk100" REFERENCE_PIN "mc_clk" FALLING;

#OFFSET = OUT AFTER "fpga_clk100" REFERENCE_PIN "mc_200_mhz_s" RISING;
#OFFSET = OUT AFTER "fpga_clk100" REFERENCE_PIN "mc_200_mhz_s" FALLING;

NET "mc_clk" TNM_NET =  "SYS_CLK";
TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK" 3.750 ns  HIGH 50 %;

#NET "u_ddr2_infrastructure/clk200_ibufg" TNM_NET = "SYS_CLK_200";
#TIMESPEC "TS_SYS_CLK_200" = PERIOD "SYS_CLK_200" 5 ns HIGH 50 %;

NET "mc_200_mhz_s" TNM_NET = "SYS_CLK_200";
TIMESPEC "TS_SYS_CLK_200" = PERIOD "SYS_CLK_200" 5 ns HIGH 50 %;



################################################################################
# I/O STANDARDS
################################################################################

NET  "ddr2_dq[*]"                                    IOSTANDARD = SSTL18_II_DCI;
NET  "DDR2_A[*]"                                     IOSTANDARD = SSTL18_II;
NET  "ddr2_ba[*]"                                    IOSTANDARD = SSTL18_II;
NET  "ddr2_ras_n"                                    IOSTANDARD = SSTL18_II;
NET  "ddr2_cas_n"                                    IOSTANDARD = SSTL18_II;
NET  "ddr2_we_n"                                     IOSTANDARD = SSTL18_II;
#NET  "ddr2_reset_n"                                  IOSTANDARD = LVCMOS18;
NET  "ddr2_cs_n"                                  IOSTANDARD = SSTL18_II;
#NET  "ddr2_cs_n[*]"                                  IOSTANDARD = SSTL18_II;
NET  "ddr2_odt[*]"                                   IOSTANDARD = SSTL18_II;
NET  "ddr2_cke"                                   IOSTANDARD = SSTL18_II;
#NET  "ddr2_cke[*]"                                   IOSTANDARD = SSTL18_II;
NET  "ddr2_dm[*]"                                    IOSTANDARD = SSTL18_II_DCI;

#NET  "sys_clk_p"                                     IOSTANDARD = LVDS_25;
#NET  "sys_clk_p" 													DIFF_TERM = TRUE; # DCI?

#NET  "sys_clk_n"                                     IOSTANDARD = LVDS_25;
#NET  "sys_clk_n" 													DIFF_TERM = TRUE;

#NET  "clk200_p"                                      IOSTANDARD = LVDS_25;
#NET  "clk200_p"													 DIFF_TERM = TRUE;

#NET  "clk200_n"                                      IOSTANDARD = LVDS_25;
#NET  "clk200_n"                                      DIFF_TERM = TRUE;

#NET  "sys_rst_n"                                     IOSTANDARD = LVCMOS18;   # system reset
#NET  "phy_init_done"                                 IOSTANDARD = LVCMOS18;
#NET  "error"                                         IOSTANDARD = LVCMOS18;
NET  "ddr2_dqs[*]"                                   IOSTANDARD = DIFF_SSTL18_II_DCI;
NET  "ddr2_dqs_n[*]"                                 IOSTANDARD = DIFF_SSTL18_II_DCI;
NET  "ddr2_ck[*]"                                    IOSTANDARD = DIFF_SSTL18_II;
NET  "ddr2_ck_n[*]"                                  IOSTANDARD = DIFF_SSTL18_II;



############################################################################
########################################################################
# Controller 0
# Memory Device: DDR2_SDRAM->SODIMMs->MT4HTF3264HY-53E #
# Data Width:     64 #
# Data Mask:     1 #
########################################################################
NET  "ddr2_a[0]"                                 LOC = "AL29" ;          #Bank
NET  "ddr2_a[1]"                                 LOC = "AL30" ;          #Bank
NET  "ddr2_a[2]"                                 LOC = "AM31" ;          #Bank
NET  "ddr2_a[3]"                                 LOC = "AL31" ;          #Bank
NET  "ddr2_a[4]"                                 LOC = "AN30" ;          #Bank
NET  "ddr2_a[5]"                                 LOC = "AM30" ;          #Bank
NET  "ddr2_a[6]"                                 LOC = "AP30" ;          #Bank
NET  "ddr2_a[7]"                                 LOC = "AP31" ;          #Bank
NET  "ddr2_a[8]"                                 LOC = "AM27" ;          #Bank
NET  "ddr2_a[9]"                                 LOC = "AP29" ;          #Bank
NET  "ddr2_a[10]"                                LOC = "AN29" ;          #Bank
NET  "ddr2_a[11]"                                LOC = "AP27" ;          #Bank
NET  "ddr2_a[12]"                                LOC = "AN27" ;          #Bank
NET  "ddr2_ba[0]"                                LOC = "AM25" ;          #Bank
NET  "ddr2_ba[1]"                                LOC = "AM26" ;          #Bank
NET  "ddr2_cas_n"                                LOC = "AP26" ;          #Bank
NET  "ddr2_ras_n"                                LOC = "AP25" ;          #Bank
NET  "ddr2_we_n"                                 LOC = "AL25" ;          #Bank
NET  "ddr2_cke"                                  LOC = "AL24" ;          #Bank
NET  "ddr2_cs_n"                                 LOC = "AM20" ;          #Bank
NET  "ddr2_odt[0]"                               LOC = "AN22" ;          #Bank
NET  "ddr2_ck_n[0]"                              LOC = "AP21" ;          #Bank
NET  "ddr2_ck[0]"                                LOC = "AP22" ;          #Bank
NET  "ddr2_ck_n[1]"                              LOC = "AP19" ;          #Bank
NET  "ddr2_ck[1]"                                LOC = "AN19" ;          #Bank
NET  "ddr2_dm[7]"                                LOC = "AB33" ;          #Bank
NET  "ddr2_dm[6]"                                LOC = "AF33" ;          #Bank
NET  "ddr2_dm[5]"                                LOC = "AF29" ;          #Bank
NET  "ddr2_dm[4]"                                LOC = "AF30" ;          #Bank
NET  "ddr2_dm[3]"                                LOC = "AJ30" ;          #Bank
NET  "ddr2_dm[2]"                                LOC = "AC25" ;          #Bank
NET  "ddr2_dm[1]"                                LOC = "AC24" ;          #Bank
NET  "ddr2_dm[0]"                                LOC = "AD26" ;          #Bank
NET  "ddr2_dqs_n[7]"                             LOC = "AJ34" ;          #Bank
NET  "ddr2_dqs[7]"                               LOC = "AH34" ;          #Bank
NET  "ddr2_dqs_n[6]"                             LOC = "AE32" ;          #Bank
NET  "ddr2_dqs[6]"                               LOC = "AD32" ;          #Bank
NET  "ddr2_dqs_n[5]"                             LOC = "Y29" ;          #Bank
NET  "ddr2_dqs[5]"                               LOC = "Y28" ;          #Bank
NET  "ddr2_dqs_n[4]"                             LOC = "AA31" ;          #Bank
NET  "ddr2_dqs[4]"                               LOC = "AB31" ;          #Bank
NET  "ddr2_dqs_n[3]"                             LOC = "AC30" ;          #Bank
NET  "ddr2_dqs[3]"                               LOC = "AB30" ;          #Bank
NET  "ddr2_dqs_n[2]"                             LOC = "AJ27" ;          #Bank
NET  "ddr2_dqs[2]"                               LOC = "AK26" ;          #Bank
NET  "ddr2_dqs_n[1]"                             LOC = "AJ29" ;          #Bank
NET  "ddr2_dqs[1]"                               LOC = "AK29" ;          #Bank
NET  "ddr2_dqs_n[0]"                             LOC = "AK27" ;          #Bank
NET  "ddr2_dqs[0]"                               LOC = "AK28" ;          #Bank
NET  "ddr2_dq[63]"                               LOC = "AE33" ;          #Bank
NET  "ddr2_dq[62]"                               LOC = "AF34" ;          #Bank
NET  "ddr2_dq[61]"                               LOC = "AE34" ;          #Bank
NET  "ddr2_dq[60]"                               LOC = "AK34" ;          #Bank
NET  "ddr2_dq[59]"                               LOC = "AK33" ;          #Bank
NET  "ddr2_dq[58]"                               LOC = "AG32" ;          #Bank
NET  "ddr2_dq[57]"                               LOC = "AJ32" ;          #Bank
NET  "ddr2_dq[56]"                               LOC = "AK32" ;          #Bank
NET  "ddr2_dq[55]"                               LOC = "AL34" ;          #Bank
NET  "ddr2_dq[54]"                               LOC = "AL33" ;          #Bank
NET  "ddr2_dq[53]"                               LOC = "AM33" ;          #Bank
NET  "ddr2_dq[52]"                               LOC = "AM32" ;          #Bank
NET  "ddr2_dq[51]"                               LOC = "AN34" ;          #Bank
NET  "ddr2_dq[50]"                               LOC = "AN33" ;          #Bank
NET  "ddr2_dq[49]"                               LOC = "AN32" ;          #Bank
NET  "ddr2_dq[48]"                               LOC = "AP32" ;          #Bank
NET  "ddr2_dq[47]"                               LOC = "W24" ;          #Bank
NET  "ddr2_dq[46]"                               LOC = "V24" ;          #Bank
NET  "ddr2_dq[45]"                               LOC = "Y26" ;          #Bank
NET  "ddr2_dq[44]"                               LOC = "W26" ;          #Bank
NET  "ddr2_dq[43]"                               LOC = "V25" ;          #Bank
NET  "ddr2_dq[42]"                               LOC = "W25" ;          #Bank
NET  "ddr2_dq[41]"                               LOC = "Y27" ;          #Bank
NET  "ddr2_dq[40]"                               LOC = "W27" ;          #Bank
NET  "ddr2_dq[39]"                               LOC = "V30" ;          #Bank
NET  "ddr2_dq[38]"                               LOC = "V28" ;          #Bank
NET  "ddr2_dq[37]"                               LOC = "V27" ;          #Bank
NET  "ddr2_dq[36]"                               LOC = "W31" ;          #Bank
NET  "ddr2_dq[35]"                               LOC = "Y31" ;          #Bank
NET  "ddr2_dq[34]"                               LOC = "W29" ;          #Bank
NET  "ddr2_dq[33]"                               LOC = "V29" ;          #Bank
NET  "ddr2_dq[32]"                               LOC = "AA29" ;          #Bank
NET  "ddr2_dq[31]"                               LOC = "AA30" ;          #Bank
NET  "ddr2_dq[30]"                               LOC = "AD30" ;          #Bank
NET  "ddr2_dq[29]"                               LOC = "AC29" ;          #Bank
NET  "ddr2_dq[28]"                               LOC = "AF31" ;          #Bank
NET  "ddr2_dq[27]"                               LOC = "AE29" ;          #Bank
NET  "ddr2_dq[26]"                               LOC = "AD29" ;          #Bank
NET  "ddr2_dq[25]"                               LOC = "AJ31" ;          #Bank
NET  "ddr2_dq[24]"                               LOC = "AK31" ;          #Bank
NET  "ddr2_dq[23]"                               LOC = "AA25" ;          #Bank
NET  "ddr2_dq[22]"                               LOC = "AA26" ;          #Bank
NET  "ddr2_dq[21]"                               LOC = "AB27" ;          #Bank
NET  "ddr2_dq[20]"                               LOC = "AC27" ;          #Bank
NET  "ddr2_dq[19]"                               LOC = "Y24" ;          #Bank
NET  "ddr2_dq[18]"                               LOC = "AA24" ;          #Bank
NET  "ddr2_dq[17]"                               LOC = "AB25" ;          #Bank
NET  "ddr2_dq[16]"                               LOC = "AB26" ;          #Bank
NET  "ddr2_dq[15]"                               LOC = "AC28" ;          #Bank
NET  "ddr2_dq[14]"                               LOC = "AB28" ;          #Bank
NET  "ddr2_dq[13]"                               LOC = "AA28" ;          #Bank
NET  "ddr2_dq[12]"                               LOC = "AG28" ;          #Bank
NET  "ddr2_dq[11]"                               LOC = "AH28" ;          #Bank
NET  "ddr2_dq[10]"                               LOC = "AE28" ;          #Bank
NET  "ddr2_dq[9]"                                LOC = "AF28" ;          #Bank
NET  "ddr2_dq[8]"                                LOC = "AH27" ;          #Bank
NET  "ddr2_dq[7]"                                LOC = "AJ26" ;          #Bank
NET  "ddr2_dq[6]"                                LOC = "AF24" ;          #Bank
NET  "ddr2_dq[5]"                                LOC = "AG25" ;          #Bank
NET  "ddr2_dq[4]"                                LOC = "AG27" ;          #Bank
NET  "ddr2_dq[3]"                                LOC = "AF25" ;          #Bank
NET  "ddr2_dq[2]"                                LOC = "AF26" ;          #Bank
NET  "ddr2_dq[1]"                                LOC = "AE27" ;          #Bank
NET  "ddr2_dq[0]"                                LOC = "AE26" ;          #Bank

###############################################################################
# Define multicycle paths - these paths may take longer because additional
# time allowed for logic to settle in calibration/initialization FSM
###############################################################################

# MIG 2.1: Eliminate Timegroup definitions for CLK0, and CLK90. Instead trace
#          multicycle paths from originating flip-flop to ANY destination
#          flip-flop (or in some cases, it can also be a BRAM)
# MUX Select for either rising/falling CLK0 for 2nd stage read capture
INST "*/u_phy_calib/gen_rd_data_sel*.u_ff_rd_data_sel" TNM = "TNM_RD_DATA_SEL";
TIMESPEC "TS_MC_RD_DATA_SEL" = FROM "TNM_RD_DATA_SEL" TO FFS
"TS_SYS_CLK" * 4;
# MUX select for read data - optional delay on data to account for byte skews
INST "*/usr_rd/gen_rden_sel_mux*.u_ff_rden_sel_mux" TNM = "TNM_RDEN_SEL_MUX";
TIMESPEC "TS_MC_RDEN_SEL_MUX" = FROM "TNM_RDEN_SEL_MUX" TO FFS
"TS_SYS_CLK" * 4;
# Calibration/Initialization complete status flag (for PHY logic only) - can
# be used to drive both flip-flops and BRAMs
INST "*/u_phy_init/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_DATA_SEL";
TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_0" = FROM "TNM_PHY_INIT_DATA_SEL" TO FFS
"TS_SYS_CLK" * 4;
# The RAM path is only used in cases where Write Latency (Additive Latency + 
# (CAS Latency - 1) + (1 in case of RDIMM)) is 2 or below. So these constraints are 
# valid for CAS Latency = 3, Additive Latency = 0 and selected part is not RDIMM. 
# If Write Latency is higher than 3, then a warning will appear in PAR, 
# and the constraint can be ignored as this path does not exist. RAM constraint 
# can be safely removed if the warning is not to be displayed.
TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_90" = FROM "TNM_PHY_INIT_DATA_SEL" TO RAMS
"TS_SYS_CLK" * 4;
# Select (address) bits for SRL32 shift registers used in stage3/stage4
# calibration
INST "*/u_phy_calib/gen_gate_dly*.u_ff_gate_dly" TNM = "TNM_GATE_DLY";
TIMESPEC "TS_MC_GATE_DLY" = FROM "TNM_GATE_DLY" TO FFS "TS_SYS_CLK" * 4;

INST "*/u_phy_calib/gen_rden_dly*.u_ff_rden_dly" TNM = "TNM_RDEN_DLY";
TIMESPEC "TS_MC_RDEN_DLY" = FROM "TNM_RDEN_DLY" TO FFS "TS_SYS_CLK" * 4;

INST "*/u_phy_calib/gen_cal_rden_dly*.u_ff_cal_rden_dly"
  TNM = "TNM_CAL_RDEN_DLY";
TIMESPEC "TS_MC_CAL_RDEN_DLY" = FROM "TNM_CAL_RDEN_DLY" TO FFS
"TS_SYS_CLK" * 4;
############################################################################### 
#The following constraint is added to prevent (false) hold time violations on
#the data path from stage1 to stage2 capture flops.  Stage1 flops are clocked by 
#the delayed DQS and stage2 flops are clocked by the clk0 clock. Placing a TIG 
#on the DQ IDDR capture flop instance to achieve this is acceptable because timing
#is guaranteed through the use of separate Predictable IP constraints. These
#violations are reported when anunconstrained path report is run.	  
############################################################################### 
INST "*/gen_dq[*].u_iob_dq/gen*.u_iddr_dq" TIG ;
###############################################################################
# DQS Read Post amble Glitch Squelch circuit related constraints
###############################################################################

###############################################################################
# LOC placement of DQS-squelch related IDDR and IDELAY elements
# Each circuit can be located at any of the following locations:
#  1. Unused "N"-side of DQS differential pair I/O
#  2. DM data mask (output only, input side is free for use)
#  3. Any output-only site
###############################################################################

###############################################################################
#The following constraint is added to avoid the HOLD violations in the trace report
#when run for unconstrained paths.These two FF groups will be clocked by two different
# clocks and hence there should be no timing analysis performed on this path.
###############################################################################
INST "*/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[*].u_en_dqs_ff" TNM = EN_DQS_FF;
TIMESPEC TS_FROM_EN_DQS_FF_TO_DQ_CE_FF = FROM EN_DQS_FF TO TNM_DQ_CE_IDDR 3.85 ns DATAPATHONLY;

INST "*/gen_dqs[0].u_iob_dqs/u_iddr_dq_ce"  LOC = "ILOGIC_X0Y43";
INST "*/gen_dqs[0].u_iob_dqs/u_iodelay_dq_ce"  LOC = "IODELAY_X0Y43";
INST "*/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce"  LOC = "ILOGIC_X0Y60";
INST "*/gen_dqs[1].u_iob_dqs/u_iodelay_dq_ce"  LOC = "IODELAY_X0Y60";
INST "*/gen_dqs[2].u_iob_dqs/u_iddr_dq_ce"  LOC = "ILOGIC_X0Y62";
INST "*/gen_dqs[2].u_iob_dqs/u_iodelay_dq_ce"  LOC = "IODELAY_X0Y62";
INST "*/gen_dqs[3].u_iob_dqs/u_iddr_dq_ce"  LOC = "ILOGIC_X0Y83";
INST "*/gen_dqs[3].u_iob_dqs/u_iodelay_dq_ce"  LOC = "IODELAY_X0Y83";
INST "*/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce"  LOC = "ILOGIC_X0Y100";
INST "*/gen_dqs[4].u_iob_dqs/u_iodelay_dq_ce"  LOC = "IODELAY_X0Y100";
INST "*/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce"  LOC = "ILOGIC_X0Y102";
INST "*/gen_dqs[5].u_iob_dqs/u_iodelay_dq_ce"  LOC = "IODELAY_X0Y102";
INST "*/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce"  LOC = "ILOGIC_X0Y136";
INST "*/gen_dqs[6].u_iob_dqs/u_iodelay_dq_ce"  LOC = "IODELAY_X0Y136";
INST "*/gen_dqs[7].u_iob_dqs/u_iddr_dq_ce"  LOC = "ILOGIC_X0Y138";
INST "*/gen_dqs[7].u_iob_dqs/u_iodelay_dq_ce"  LOC = "IODELAY_X0Y138";

###############################################################################
# LOC and timing constraints for flop driving DQS CE enable signal
# from fabric logic. Even though the absolute delay on this path is
# calibrated out (when synchronizing this output to DQS), the delay
# should still be kept as low as possible to reduce post-calibration
# voltage/temp variations - these are roughly proportional to the
# absolute delay of the path.                                    
#	The following code has been commented for V5 as the predictable IP will take 
#	care of placement of these flops by meeting the MAXDELAY requirement.  
#	These constraints will be removed in the next release.  
###############################################################################

INST "*/u_phy_calib/gen_gate[0].u_en_dqs_ff"  LOC = SLICE_X0Y29;
INST "*/u_phy_calib/gen_gate[1].u_en_dqs_ff"  LOC = SLICE_X0Y30;
INST "*/u_phy_calib/gen_gate[2].u_en_dqs_ff"  LOC = SLICE_X0Y31;
INST "*/u_phy_calib/gen_gate[3].u_en_dqs_ff"  LOC = SLICE_X0Y49;
INST "*/u_phy_calib/gen_gate[4].u_en_dqs_ff"  LOC = SLICE_X0Y50;
INST "*/u_phy_calib/gen_gate[5].u_en_dqs_ff"  LOC = SLICE_X0Y51;
INST "*/u_phy_calib/gen_gate[6].u_en_dqs_ff"  LOC = SLICE_X0Y68;
INST "*/u_phy_calib/gen_gate[7].u_en_dqs_ff"  LOC = SLICE_X0Y69;

# Control for DQS gate - from fabric flop. Prevent "runaway" delay -
# two parts to this path: (1) from fabric flop to IDELAY, (2) from
# IDELAY to asynchronous reset of IDDR that drives the DQ CE's
# This can be relaxed by the user for lower frequencies:
# 300MHz = 850ps, 267MHz = 900ps. At 200MHz = 950ps.
# In general PAR should be able to route this
# within 900ps over all speed grades.
NET "*/u_phy_io/en_dqs[*]" MAXDELAY = 600 ps;
NET "*/u_phy_io/gen_dqs*.u_iob_dqs/en_dqs_sync" MAXDELAY = 850 ps;

###############################################################################
# "Half-cycle" path constraint from IOB flip-flop to CE pin for all DQ IDDR's
# for DQS Read Post amble Glitch Squelch circuit
###############################################################################

# Max delay from output of IOB flip-flop to CE input of DQ IDDRs =
#  tRPST + some slack where slack account for rise-time of DQS on board.
#  For now assume slack = 0.400ns (based on initial SPICE simulations,
#  assumes use of ODT), so time = 0.4*Tcyc + 0.40ns = 1.6ns @333MHz
INST "*/gen_dqs[*].u_iob_dqs/u_iddr_dq_ce" TNM = "TNM_DQ_CE_IDDR";
INST "*/gen_dq[*].u_iob_dq/gen_stg2_*.u_iddr_dq" TNM = "TNM_DQS_FLOPS";
TIMESPEC "TS_DQ_CE" = FROM "TNM_DQ_CE_IDDR" TO "TNM_DQS_FLOPS" 1.9 ns;

 

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Contributor
Contributor
9,034 Views
Registered: ‎07-24-2012

Re: MIG 3.6 DDR2 design doesn't meet all timing constraints

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This is the report I get from MIG when I generate the DDR2 core

 

CORE Generator Options:
   Target Device                  : xc5vfx100t-ff1136
   Speed Grade                    : -1
   HDL                            : vhdl
   Synthesis Tool                 : ISE

If any of the above options are incorrect, please click on "Cancel", change the Project Options in XPS, and re-run MIG from the MPMC GUI

MIG Output Options:
   Module Name                    : mig_v3_6
   No of Controllers              : 1
   Selected Compatible Device(s)  : --
   
   PPC440                         : enabled
   PowerPC440 Block Selection     : Bottom

FPGA Options:
   PLL                            : enabled
   Debug Signals                  : Disable
   System Clock                   : Differential
   Limit to 2 Bytes per Bank      : disabled

Extended FPGA Options:
   DCI for DQ/DQS                 : enabled
   DCI for Address/Control        : disabled
   Class for Address and Control  : Class II

Reserve Pins:
   --
    
   /*******************************************************/
   /*                  Controller 0                       */
   /*******************************************************/
   Controller Options :
      Memory                         : DDR2_SDRAM
      Design Clock Frequency         : 3750 ps(266.67 MHz)
      Memory Type                    : SODIMMs
      Memory Part                    : MT4HTF3264HY-53E
      Equivalent Part(s)             : --
      Data Width                     : 64
      Memory Depth                   : 1
      ECC                            : ECC Disabled
      Data Mask                      : enabled

   Memory Options:
      Burst Length (MR[2:0])         : 4(010)
      Burst Type (MR[3])             : sequential(0)
      CAS Latency (MR[6:4])          : 4(100)
      Output Drive Strength (EMR[1]) : Fullstrength(0)
      RTT (nominal) - ODT (EMR[6,2]) : 75ohms(01)
      Additive Latency (EMR[5:3])    : 0(000)

   FPGA Options:
      IODELAY Performance Mode       : HIGH

   Bank Selections:
    Data:               Bank 13,17,21
    Address/Control:    Bank 17,21,25
    System Control:     Bank 13
    System Clock:       Bank 4

 

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Re: MIG 3.6 DDR2 design doesn't meet all timing constraints

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I can reduce the number of failures to 1 by

changing some values in the UCF to:

# for 266MHz

NET "*/u_phy_io/en_dqs[*]" MAXDELAY = 900 ps;
NET "*/u_phy_io/gen_dqs*.u_iob_dqs/en_dqs_sync" MAXDELAY = 900 ps;

# bump previous value by 0.5 ns

TIMESPEC "TS_DQ_CE" = FROM "TNM_DQ_CE_IDDR" TO "TNM_DQS_FLOPS" 1.95 ns;

 

I am attaching the new timing report

 

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Re: MIG 3.6 DDR2 design doesn't meet all timing constraints

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I am not sure how to reduce the delay here. Any insights?

 

Timing constraint: TS_cobo_clks_cobo_clks_SIG_PLL0_CLKOUT3 = PERIOD TIMEGRP         "cobo_clks_cobo_clks_SIG_PLL0_CLKOUT3" TS_sys_clk_pin / 2.66666667         HIGH 50%; 
  4646 paths analyzed, 1989 endpoints analyzed, 201 failing endpoints 
  201 timing errors detected. (201 setup errors, 0 hold errors, 0 component switching limit errors) 
  Minimum period is   5.125ns. 
 -------------------------------------------------------------------------------- 
  
 Paths for end point ppc440_0/ppc440_0/PPC440_i (PPC440_X0Y1.MCMIREADDATA38), 1 path 
 -------------------------------------------------------------------------------- 
 Slack (setup path):     -1.375ns (requirement - (data path - clock path skew + uncertainty)) 
   Source:               u_ddr2_top/u_ddr2_top/u_ddr2_top/u_mem_if_top/u_usr_top/usr_rd/.gen_rdf[0].u_rdf (RAM) 
   Destination:          ppc440_0/ppc440_0/PPC440_i (CPU) 
   Requirement:          3.750ns 
   Data Path Delay:      5.003ns (Levels of Logic = 0) 
   Clock Path Skew:      -0.047ns (1.797 - 1.844) 
   Source Clock:         mc_clk rising at 0.000ns 
   Destination Clock:    mc_clk rising at 3.750ns 
   Clock Uncertainty:    0.075ns 
  
   Clock Uncertainty:          0.075ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE 
     Total System Jitter (TSJ):  0.070ns 
     Discrete Jitter (DJ):       0.132ns 
     Phase Error (PE):           0.000ns 
  
   Maximum Data Path: u_ddr2_top/u_ddr2_top/u_ddr2_top/u_mem_if_top/u_usr_top/usr_rd/.gen_rdf[0].u_rdf to ppc440_0/ppc440_0/PPC440_i 
     Location                   Delay type         Delay(ns)  Physical Resource 
                                                              Logical Resource(s) 
     -------------------------------------------------------  ------------------- 
     RAMB36_X1Y16.DOBDOL3       Trcko_DOB             0.818   u_ddr2_top/u_ddr2_top/u_ddr2_top/u_mem_if_top/u_usr_top/usr_rd/.gen_rdf[0].u_rdf 
                                                              u_ddr2_top/u_ddr2_top/u_ddr2_top/u_mem_if_top/u_usr_top/usr_rd/.gen_rdf[0].u_rdf 
     PPC440_X0Y1.MCMIREADDATA38 net (fanout=1)        3.252   ppc440_0_PPC440MC_MCMIREADDATA<38> 
     PPC440_X0Y1.CPMMCCLK       Tppcdck_MCM           0.933   ppc440_0/ppc440_0/PPC440_i 
                                                              ppc440_0/ppc440_0/PPC440_i 
     -------------------------------------------------------  --------------------------- 
     Total                                            5.003ns (1.751ns logic, 3.252ns route) 
                                                              (35.0% logic, 65.0% route) 
  
 -------------------------------------------------------------------------------- 

 

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Re: MIG 3.6 DDR2 design doesn't meet all timing constraints

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I couldn't solve this issue. I had to reduce my clock speed from 266MHz to 200 and change the following to get it to pass.

 

TIMESPEC "TS_SYS_CLK" = PERIOD "mc_clk" 5.000 ns;

NET "*/u_phy_io/en_dqs[*]" MAXDELAY = 900 ps;
NET "*/u_phy_io/gen_dqs*.u_iob_dqs/en_dqs_sync" MAXDELAY = 900 ps;

TIMESPEC "TS_DQ_CE" = FROM "TNM_DQ_CE_IDDR" TO "TNM_DQS_FLOPS" 2.1 ns;

 

 

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Re: MIG 3.6 DDR2 design doesn't meet all timing constraints

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I am still debugging why it is not working at 266MHz.. I got it down to 1 constraint after adding these

 

INST "*/PPC440_i" LOC  = PPC440_X0Y0;
INST "*/.gen_rdf[0].u_rdf" LOC  = RAMB36_X0Y11;
INST "*/.gen_rdf[0].u_rdf1" LOC = RAMB36_X0Y10;
INST "*/.gen_wdf[0].u_usr_wr_fifo/.u_wdf" LOC = RAMB36_X0Y9;
INST "*/.gen_wdf[1].u_usr_wr_fifo/.u_wdf" LOC = RAMB36_X0Y8;

 

Here is the last failure:

 

----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
                                            |             |    Slack   | Achievable | Errors |    Score   
----------------------------------------------------------------------------------------------------------
* TS_cobo_clks_cobo_clks_SIG_PLL0_CLKOUT3 = | SETUP       |    -0.064ns|     3.813ns|       2|          91
   PERIOD TIMEGRP         "cobo_clks_cobo_c | HOLD        |     0.066ns|            |       0|           0
  lks_SIG_PLL0_CLKOUT3" TS_xtal_clk / 2.666 |             |            |            |        |            
  66667 HIGH         50%                    |             |            |            |        |            
----------------------------------------------------------------------------------------------------------



 Timing constraint: TS_cobo_clks_cobo_clks_SIG_PLL0_CLKOUT3 = PERIOD TIMEGRP         "cobo_clks_cobo_clks_SIG_PLL0_CLKOUT3" TS_xtal_clk / 2.66666667 HIGH         50%; 
  4646 paths analyzed, 1985 endpoints analyzed, 1 failing endpoint 
  1 timing error detected. (1 setup error, 0 hold errors, 0 component switching limit errors) 
  Minimum period is   3.835ns. 
 -------------------------------------------------------------------------------- 
  
 Paths for end point ppc440_0/ppc440_0/PPC440_i (PPC440_X0Y0.MCMIADDRREADYTOACCEPT), 1 path 
 -------------------------------------------------------------------------------- 
 Slack (setup path):     -0.085ns (requirement - (data path - clock path skew + uncertainty)) 
   Source:               u_ddr2_top/u_ddr2_top/u_ddr2_top/u_mem_if_top/u_u_ctrl/mc_mi_addr_rdy_accpt_r (FF) 
   Destination:          ppc440_0/ppc440_0/PPC440_i (CPU) 
   Requirement:          3.750ns 
   Data Path Delay:      3.471ns (Levels of Logic = 0) 
   Clock Path Skew:      -0.289ns (1.700 - 1.989) 
   Source Clock:         mc_clk rising at 0.000ns 
   Destination Clock:    mc_clk rising at 3.750ns 
   Clock Uncertainty:    0.075ns 
  
   Clock Uncertainty:          0.075ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE 
     Total System Jitter (TSJ):  0.070ns 
     Discrete Jitter (DJ):       0.132ns 
     Phase Error (PE):           0.000ns 
  
   Maximum Data Path: u_ddr2_top/u_ddr2_top/u_ddr2_top/u_mem_if_top/u_u_ctrl/mc_mi_addr_rdy_accpt_r to ppc440_0/ppc440_0/PPC440_i 
     Location                          Delay type         Delay(ns)  Physical Resource 
                                                                     Logical Resource(s) 
     --------------------------------------------------------------  ------------------- 
     SLICE_X31Y19.DQ                   Tcko                  0.450   ppc440_0_PPC440MC_MCMIADDRREADYTOACCEPT 
                                                                     u_ddr2_top/u_ddr2_top/u_ddr2_top/u_mem_if_top/u_u_ctrl/mc_mi_addr_rdy_accpt_r 
     PPC440_X0Y0.MCMIADDRREADYTOACCEPT net (fanout=3)        2.080   ppc440_0_PPC440MC_MCMIADDRREADYTOACCEPT 
     PPC440_X0Y0.CPMMCCLK              Tppcdck_MCM           0.941   ppc440_0/ppc440_0/PPC440_i 
                                                                     ppc440_0/ppc440_0/PPC440_i 
     --------------------------------------------------------------  --------------------------- 
     Total                                                   3.471ns (1.391ns logic, 2.080ns route) 
                                                                     (40.1% logic, 59.9% route) 

 

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Re: MIG 3.6 DDR2 design doesn't meet all timing constraints

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I have just updated from 12.3 to 13.4 and everything passed!

The only thing I had to change was  clock_generator version

 

Now I am using  PARAMETER HW_VER = 4.03.a instead of 4.00

 

 

 

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