03-22-2011 04:46 PM
I have a problem with the output phase of the MMCM (DCM) in simulation. I am simulating the very simple scheme of "clock deskew"using MMCM. Based on UG, the CLKIN1 and CLKFBIN must be aligned but, in my simulation, they are not aligned and CLKFBIN is some amount of time behind CLKIN1. I ran the simulation several times and looks like the time difference between CLKIN1 and CLKFBIN is exactly equivalent to the VCO clock period. BTW, I tried both the "zhold" and "internal" compensations but the results are the same. Would you please let me know why am I seeing this phase difference?
03-23-2011 07:29 AM
There is an bug in the behavourial simulation model in 12.4 that caused the outputs to be misaligned. This was fixed in 13.1.
What version of SW are you using?
03-23-2011 07:55 AM
I am using the version 12.4. So the simulator has a problem not the block itself? Will I still see the phase difference in real implementation using 12.4 version?
03-23-2011 08:09 AM
The issue was only with the behavourial simulation the hardware would function as expected.
07-04-2011 02:55 AM - edited 07-04-2011 02:59 AM
I've the same problem as ppaysarvi. Output clock phases of MMCM_ADV Xilinx primitive are not as expected in behavioral and post-route simulations. I've followed your advice and I've tried with ISE 13.1but this problem remains the same. I've verified in implementing on hardware the MMCM_ADV and output clocks are correct.
It seems that ISE 13.1 doesn't correct this bug. Anyone would have a solution to solve this problem ?
Thanks for your help,
07-05-2011 07:11 AM
07-07-2011 01:55 AM
Thanks for your answer rcingham,
I use the MMCM_ADV primitive. But I've tested the use of Clocking Wizard in the CoreGen available with ISE 13.1 but the problem is similar. In functionnal and post-route simulation, output frequencies are correct but output phases (for example, I expect a 90° phase on a CLKOUT3 but it generates a in-phase CLKOUT3). I've tested this IP generated by Clocking Wizard CoreGen on a board and all output phases are as expected !
This issue is known by Xilinx for ISE 12.4. Would it be a similar bug with ISE 13.1 ?
07-07-2011 03:17 AM
11-24-2011 02:15 AM