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Visitor
Visitor
12,299 Views
Registered: ‎03-20-2015

Memory Controller (MIG and MPMC)

I would like implement a memory controller, with concurrent access, on a ML605 board (Virtex-6).

To do this, I saw 2 applications notes :

  • XTP047 “MIG Design Creation” but I’m not sure that can do concurrent access with this IP.
  • XAPP739 “AXI Multi-Ported Memory Controller” but how I realize the interface between my own process vhdl and the IP AXI Interconnect?

 

Thank you in advance

 

Renaud

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Xilinx Employee
Xilinx Employee
12,284 Views
Registered: ‎07-31-2012

Hi,

 

By concurrent access do you mean same controller to control two DDR's at the same time?

 

Thanks,
Anirudh

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Xilinx Employee
Xilinx Employee
12,242 Views
Registered: ‎02-06-2013

Hi

 

Standalone MIG generated using xtp047 cannot do concurrent access as ports cannot be enabled in virtex6,You should be following xapp739 to have concurrent access and replace the axi vdma with your logic to controll the axi interconnect.

Regards,

Satish

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Visitor
Visitor
12,215 Views
Registered: ‎03-20-2015

Thanks for your feedback,

 

With concurrent access, I mean that different devices share a common memory controller and can access the DDR at the same time.

 

To do this, I follow the xapp739 and it recommends to “Enable AXI Interface” (MIG IP Core). However, to enable this option, the language must be “Verilog”. It is necessary? If yes, can I mix vhdl and Verilog languages in a Xilinx Design? A specific license is necessary?

After, you mention that I need to replace the axi vdma with my logic to control the axi interconnect. How to access MPMC with Custom IP using AXI bus?

 

 

Thanks

Renaud

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Xilinx Employee
Xilinx Employee
12,206 Views
Registered: ‎02-06-2013

Hi

 

Yes axi interface is available only when verilog is selected.

 

You can use mixed language VHDL and Verilog modules in your desing and you don't require a special license for it.

Regards,

Satish

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Visitor
Visitor
12,065 Views
Registered: ‎04-03-2015

Hi,

I am working on MIG for virtex 6.I am following the documentation in XAPP739, in this case the design mentioned has axi interconnect with MIG and DDR3 ram so can I add the processor and one more custom peripheral to the same design?

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Xilinx Employee
Xilinx Employee
12,012 Views
Registered: ‎02-06-2013

Hi

 

Yes you can do that.

Regards,

Satish

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Visitor
Visitor
12,006 Views
Registered: ‎04-03-2015

Thanks Satish,

 

In the MIG design purposed in Xapp 739 could you please let me know the how I can connect Microblaze to AXI intercoonect  in ISE?

Or is there any documentation for the ports which needs to be connected for the same?

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