03-20-2015 06:37 AM
I would like implement a memory controller, with concurrent access, on a ML605 board (Virtex-6).
To do this, I saw 2 applications notes :
Thank you in advance
03-20-2015 10:53 AM
By concurrent access do you mean same controller to control two DDR's at the same time?
03-22-2015 01:34 PM - edited 03-22-2015 01:34 PM
Standalone MIG generated using xtp047 cannot do concurrent access as ports cannot be enabled in virtex6,You should be following xapp739 to have concurrent access and replace the axi vdma with your logic to controll the axi interconnect.
03-23-2015 09:43 AM
Thanks for your feedback,
With concurrent access, I mean that different devices share a common memory controller and can access the DDR at the same time.
To do this, I follow the xapp739 and it recommends to “Enable AXI Interface” (MIG IP Core). However, to enable this option, the language must be “Verilog”. It is necessary? If yes, can I mix vhdl and Verilog languages in a Xilinx Design? A specific license is necessary?
After, you mention that I need to replace the axi vdma with my logic to control the axi interconnect. How to access MPMC with Custom IP using AXI bus?
03-23-2015 12:09 PM
Yes axi interface is available only when verilog is selected.
You can use mixed language VHDL and Verilog modules in your desing and you don't require a special license for it.
04-03-2015 09:59 PM
04-06-2015 11:17 AM
Yes you can do that.
04-06-2015 12:26 PM