UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer wooshishui
Observer
1,629 Views
Registered: ‎07-16-2008

Multiplexing between two DCM generated clocks (XC4CF100-11ff1152)

Can somebody help me?

 

The problem is to use a BUFGMUX to multiplex two clocks, 25 MHz and 75 MHz.

 

The 25 MHz clock is generated by DCM by using a Divided DCM CLK out (clkdv).

However the 75 MHz is also generated by DCM but by using the DCM CLK synthesis out (M/D) (clkfx).

The two clock outputs are connected to a  BUFGMUX and the multiplexed clock (mux_clk) drive an aynchronous 

FIFO  to read the data out (fifo_dout). The connection is the same as Clock Switching Between Two DCMs

which is shown in Figure 2-14, page 88, Virtex 4 FPGA User Guide.

 

Before the data is transmitted out of the FPGA, the data fifo_dout

is through a small pipeline stage, which is synchronized by the clock mux_clk.

 

But is show the me the different results by switching the two clocks above.

 

1. By selecting clock 25 MHz the data transfer is very stable.

2. By selecting clock 75 MHz the data transfer is in confusion.

 

The results are measured by Logic Analyzer. The table below is from the *.par file.

 

+-------------------------------+-------------+-------------+-------------+-------------+-------------+--------------+-------------+
|                                                |   Period         |       Actual Period               |      Timing Errors                 |      Paths Analyzed       |
|           Constraint                     | Requirement  |-------------+--------------|-------------+-------------- |-------------+-----------------|
|                                                |                      |   Direct     | Derivative        |   Direct    | Derivative          |   Direct    | Derivative   |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+--------------+-------------+
|TS_CLK_125MHz                 |      8.000ns    |      7.891ns|         4.375ns  |                      0|                 0|            221836|         1084|
| TS_MC1                                |     16.000ns   |      2.238ns|               N/A |                      0|                 0|               48|                0|
| *dcm_ps_clk_o_1_clkdv        |    40.000ns    |      2.220ns|              N/A |                      0|                  0|                 0|                0|
| *dcm_ps_clk_o_0_clkfx         |     13.333ns   |      7.291ns|              N/A |                      0|                  0|           1036|                0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+---------------+

 

What i doesn't understand in the report is why in the column  Direct of Paths Analyzed 0  for clkdv (25 MHz) and 1036

for clkfx  (75MHz). Can somebody tell me the diffrence between them?

 

 

thanks in advance.

 

woo

Message Edited by wooshishui on 04-22-2010 09:15 AM
0 Kudos