12-17-2013 07:41 AM
I have insert GTH transceiver into my project. When I try to implement the design I have next critical warnings:
I have tryed to manually routing these nets like in example_ip_project. After routing, I receive 976 overlaps, bad timing and many other unrouted nets.
What should I do?
12-18-2013 11:00 AM
12-19-2013 05:12 AM
In accordingly with placement
These signals used only for clocking gt0_txpmaresetdone_out, gt0_rxpmaresetdone_out and so on for 1, 2, and 3 transmitters.
May be I should use set_false_path for leds and jtag clock?
I use X1Y36-39 transmitters. I think that some elements (BUFG and PLLE2_ADV) is placed far away from transmitters.
How can I change location of some elements (I mean BUFG and PLLE2_ADV)?
12-19-2013 06:46 PM
Have you instantiated clock buffers on these clock outputs of the GTH? The output clocks of the GTH have dedicated connections to the clocking resources within the FPGA (BUFG, BUFH and maybe even BUFR, I am not sure and I think it depends on the device). The diagram you attached seems to show a direct connection from the GTH to some slices - if this really is the rxoutclk_out nets, then they are probably structurally unroutable without a clock buffer.
12-23-2013 01:13 AM
01-20-2014 04:25 AM
Thank you for reply! The initial design with gth transmitter was with RXOUTCLK. I connect RXUSRCLK instead of RXOUTCLK in gtwizard_0_init module and design was fully routed.