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Visitor nikita1584
Visitor
10,438 Views
Registered: ‎10-10-2013

Nets rxoutclk/txoutclk is not completely routed

I have insert GTH transceiver into my project. When I try to implement the design I have next critical warnings:

 

6 net(s) are unrouted. The problem net(s) are gt1_rxoutclk_out, gt1_txoutclk_out, gt2_rxoutclk_out, gt2_txoutclk_out, gt3_rxoutclk_out, gt3_txoutclk_out.

 

2 net(s) are partially routed. The problem net(s) are gt0_rxoutclk_out, gt0_txoutclk_out.

 

I have tryed to manually routing these nets like in example_ip_project. After routing, I receive 976 overlaps, bad timing and many other unrouted nets.

 

What should I do?

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5 Replies
Moderator
Moderator
10,420 Views
Registered: ‎02-16-2010

Re: Nets rxoutclk/txoutclk is not completely routed

Please give more details on how you are using these signals in your design..This could help understand the reason for unroutability by the tool...
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Visitor nikita1584
Visitor
10,405 Views
Registered: ‎10-10-2013

Re: Nets rxoutclk/txoutclk is not completely routed

In accordingly with placement

 

Снимок экрана из 2013-12-19 15:57:53.png

 

These signals used only for clocking gt0_txpmaresetdone_out, gt0_rxpmaresetdone_out and so on for 1, 2, and 3 transmitters.

 

May be I should use set_false_path for leds and jtag clock?

 

I use X1Y36-39 transmitters. I think that some elements (BUFG and PLLE2_ADV) is placed far away from transmitters.

 

How can I change location of some elements (I mean BUFG and PLLE2_ADV)?

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Historian
Historian
10,391 Views
Registered: ‎01-23-2009

Re: Nets rxoutclk/txoutclk is not completely routed

Have you instantiated clock buffers on these clock outputs of the GTH? The output clocks of the GTH have dedicated connections to the clocking resources within the FPGA (BUFG, BUFH and maybe even BUFR, I am not sure and I think it depends on the device). The diagram you attached seems to show a direct connection from the GTH to some slices - if this really is the rxoutclk_out nets, then they are probably structurally unroutable without a clock buffer.

 

Avrum

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Moderator
Moderator
10,365 Views
Registered: ‎02-16-2010

Re: Nets rxoutclk/txoutclk is not completely routed

The diagram does not help the usage. It would help if provide the connections going from these signals to your design.

usually it is like txoutclk/rxoutclk -> bufg (mandatory) -> mmcm (not mandatory) -> GT/user logic.

Can you provide the critical warning message? This could help understand the reason for the warning...
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Visitor nikita1584
Visitor
10,313 Views
Registered: ‎10-10-2013

Re: Nets rxoutclk/txoutclk is not completely routed

Thank you for reply! The initial design with gth transmitter was with RXOUTCLK. I connect RXUSRCLK instead of RXOUTCLK in gtwizard_0_init module and design was fully routed.

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