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Visitor arcpage
Visitor
2,877 Views
Registered: ‎05-16-2011

NgdBuild Error HW Cosimulation

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Hello !

 

I'm writing a simple design in order to test the different possibilities of HW Co-Simulation on ML605. I work on ISE 13.1.

I try to make an hybrid design with an external clock in which there is a FIFO. One side of the FIFO is controlled by the embedded design clocked by a MMCM connected to the external differential clock of the ML605. The other side is controlled by the test bench running on my computer in which the clock is emulated. The purpose is simple : the embedded side writes in the FIFO since rst is low. The simulated part reads on the other part.

 

My code is :

 

 

entity readfifo is

  port (
    clkr          : in  std_logic;
    clkw_P        : in std_logic;
    clkw_N        : in std_logic;
    rst           : in  std_logic;
    rd_en         : in  std_logic;
    rd_data_count : out std_logic_vector(9 downto 0);
    datar         : out std_logic_vector(31 downto 0));

end readfifo;

architecture beh of readfifo is

  -- Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
  -- Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
  ------------------------------------------------------------------------------
  -- CLK_OUT1    10.000      0.000      50.0      178.053     89.971
  --
  ------------------------------------------------------------------------------
  -- Input Clock   Input Freq (MHz)   Input Jitter (UI)
  ------------------------------------------------------------------------------
  -- primary         200.000            0.010

  component clk_wiz_v3_1
    port
      (                                 -- Clock in ports
        CLK_IN1_P : in  std_logic;
        CLK_IN1_N : in  std_logic;
        -- Clock out ports
        CLK_OUT1  : out std_logic
        );
  end component;

  component fifo
    port (
      rst           : in  std_logic;
      wr_clk        : in  std_logic;
      rd_clk        : in  std_logic;
      din           : in  std_logic_vector(31 downto 0);
      wr_en         : in  std_logic;
      rd_en         : in  std_logic;
      dout          : out std_logic_vector(31 downto 0);
      full          : out std_logic;
      empty         : out std_logic;
      rd_data_count : out std_logic_vector(9 downto 0)
      );
  end component;

  signal clkw     : std_logic;
  signal rd_clk_i : std_logic;
  signal din_i    : std_logic_vector(31 downto 0);
  signal wr_en_i  : std_logic;
  signal dout_i   : std_logic_vector(31 downto 0);
  signal full_i   : std_logic;
  signal empty_i  : std_logic;


begin  -- beh


  clk_wiz_v3_11 : clk_wiz_v3_1
    port map
    (                                   -- Clock in ports
      CLK_IN1_P => clkw_P,
      CLK_IN1_N => clkw_N,
      -- Clock out ports
      CLK_OUT1  => clkw);

  fifo1 : fifo
    port map (
      rst           => rst,
      wr_clk        => clkw,
      rd_clk        => clkr,
      din           => din_i,
      wr_en         => wr_en_i,
      rd_en         => rd_en,
      dout          => dout_i,
      full          => open,
      empty         => open,
      rd_data_count => rd_data_count
      );

  pwrite : process (clkw)
  begin  -- process read
    if clkr'event and clkr = '1' then   -- rising clock edge
      if rst = '1' then                 -- synchronous reset (active high)
        din_i   <= (others => '0');
        wr_en_i <= '0';
      else
        din_i   <= din_i + 1;
        wr_en_i <= '1';
      end if;
    end if;
  end process pwrite;

  datar <= dout_i;

end beh;

 

 

My test bench is :

 

 

entity readfifo_tb is
end readfifo_tb;

-------------------------------------------------------------------------------

architecture beh of readfifo_tb is

  component readfifo
    port (
      clkr          : in  std_logic;
      clkw_P        : in  std_logic;
      clkw_N        : in  std_logic;
      rst           : in  std_logic;
      rd_en         : in  std_logic;
      rd_data_count : out std_logic_vector(9 downto 0);
      datar         : out std_logic_vector(31 downto 0));
  end component;

  signal clkr_i          : std_logic := '0';
  signal clkw_P_i        : std_logic := '0';
  signal clkw_N_i        : std_logic := '1';
  signal rst_i           : std_logic;
  signal rd_en_i         : std_logic;
  signal rd_data_count_i : std_logic_vector(9 downto 0);
  signal datar_i         : std_logic_vector(31 downto 0);

begin  -- beh

  DUT : readfifo
    port map (
      clkr          => clkr_i,
      clkw_P        => clkw_P_i,
      clkw_N        => clkw_N_i,
      rst           => rst_i,
      rd_en         => rd_en_i,
      rd_data_count => rd_data_count_i,
      datar         => datar_i);

  clkr_i <= not(clkr_i) after 50 ns;
  
  reset : process
  begin
    rst_i <= '0';
    wait for 100 ns;
    rst_i <= '1';
  end process reset;

  pread : process (clkr_i)
  begin  -- process read
    if clkr_i'event and clkr_i = '1' then  -- rising clock edge
      if rst_i = '1' then                  -- synchronous reset (active low)
        rd_en_i <= '0';
      else
        rd_en_i <= '1';
      end if;
    end if;
  end process pread;


end beh;

 

 

My UCF :

 

 

NET */clkw_P		LOC = "J9";
NET */clkw_N 		LOC = "H9";

 

My compile file :

 

 

fuse -intstyle ise -prj readfifo_tb_beh.prj -hwcosim_instance /readfifo_tb/DUT -hwcosim_clock clkr -hwcosim_board ml605-jtag -hwcosim_incremental 1 -hwcosim_constraints ./src/const.ucf work.readfifo_tb -o readfifo_hwcosim.exe

 

 

I don't know why I have these errors :

 

 

ERROR:NgdBuild:455 - logical net 'hwcif/hwcosim_memory_map_inst/int_o_clkw_n'
   has multiple driver(s):
     pin Q on block hwcif/hwcosim_memory_map_inst/int_o_clkw_n with type FD,
     pin PAD on block hwcif/hwcosim_memory_map_inst/int_o_clkw_n.PAD with type
   PAD
ERROR:NgdBuild:924 - input pad net 'hwcif/hwcosim_memory_map_inst/int_o_clkw_n'
   is driving non-buffer primitives:
     pin I1 on block hwcif/hwcosim_memory_map_inst/int_o_clkw_n_rstpot with type
   LUT3,
     pin Q on block hwcif/hwcosim_memory_map_inst/int_o_clkw_n with type FD
ERROR:NgdBuild:455 - logical net 'hwcif/hwcosim_memory_map_inst/int_o_clkw_p'
   has multiple driver(s):
     pin Q on block hwcif/hwcosim_memory_map_inst/int_o_clkw_p with type FD,
     pin PAD on block hwcif/hwcosim_memory_map_inst/int_o_clkw_p.PAD with type
   PAD
ERROR:NgdBuild:924 - input pad net 'hwcif/hwcosim_memory_map_inst/int_o_clkw_p'
   is driving non-buffer primitives:
     pin I1 on block hwcif/hwcosim_memory_map_inst/int_o_clkw_p_rstpot with type
   LUT3,
     pin Q on block hwcif/hwcosim_memory_map_inst/int_o_clkw_p with type FD

 

 

I quote the ug818 page 17 :

 

"If a clock port is mapped to an FPGA IOB via a LOC constraint, the logic driven by this clock belongs to the free-running portion. If a clock port has no LOC constraint assigned, the hardware co-simulation interface toggles the value on this port when a corresponding clock event occurs in the test bench."

 

 

Isim wants to connect clkw_N to the Q output of a FD but I put a constraint on it...

 

Could anyone help me ?

 

Thanks.

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Visitor arcpage
Visitor
3,512 Views
Registered: ‎05-16-2011

Re: NgdBuild Error HW Cosimulation

Jump to solution

I found my mistake :

- the name of the UCF file must be the same as the instance co-simulated.

- NET "net_name" LOC = - - .

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1 Reply
Visitor arcpage
Visitor
3,513 Views
Registered: ‎05-16-2011

Re: NgdBuild Error HW Cosimulation

Jump to solution

I found my mistake :

- the name of the UCF file must be the same as the instance co-simulated.

- NET "net_name" LOC = - - .

0 Kudos