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11,936 Views
Registered: ‎05-09-2014

OBUFT Not Working As Expected

I'm using an OBUFT as follows:

 

tel_bb_mux <= tel_bb_buf_enb when (tel_bb_mux_enb = '0') else led_ctr(15);

obuft_0 : OBUFT port map (O => io_pwr_buf_en_io, I => tel_bb_mux, T => io_pwr_buf_en);

If I generate a .bit file using the Chipscope Inserter to inspect the above signals the I/O pin io_pwr_buf_en_io works as expected.  If I generate a .bit file without using the Chipscope Inserter the I/O pin doesn't work.  All control signals come from registers written by my local processor.

 

    After generating the non-Chipscope Inserter .bit file I imported the project into planAhead and everything is there.  According to planAhead both version of the FPGA look the same regarding the structure of the I/O pin.

 

 

    How do I get the I/O pin io_pwr_buf_en_io to work without using the Chipscope Inserter?  I'm using Rev 13.2 of the software.

 

    Thanks

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Registered: ‎02-25-2008

Why aren't you doing:

 

io_pwr_buf_en_io <= tel_bb_mux when io_pwr_buf_en = '1' else 'Z';

 

??

----------------------------Yes, I do this for a living.
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Registered: ‎05-09-2014

bassman59:

 

     Thanks for your reponse.  The equation listed in my first post was just one of many different versions.  I've also tried


1 - io_pwr_buf_en_io    <= 'Z' when (io_pwr_buf_en = '1') else tel_bb_buf_enb;

 

2 - io_pwr_buf_en_io    <= tel_bb_buf_enb when (io_pwr_buf_en = '0') else 'Z';

 

    I also tried ANDing all control signals together and routing this new signal to an unused output pin.  I was trying to see if this new signal changed the timing of the signals just like inserting the Chipscope core would.

 

     In each case none of the FPGAs worked.  My guess is that inserting a Chipscope core changes the internal timing of the device that make it work. I've already gone through the Synthesis, MAP, PAR and timing reports without any errors or warnings related to this function.  The register that feeds the OBUFT are within a clock domain that has a clock contraint, no timing errors are reported.  I've also verified that I am writting the correct registers in simulation, all seem good.

 

     Any new ideas are welcome.

 

        Thanks

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Registered: ‎02-25-2008


@marvinscheinbart wrote:

 

     In each case none of the FPGAs worked. 


Describe "worked" and "didn't work."

----------------------------Yes, I do this for a living.
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Registered: ‎05-09-2014

     What I mean by not working is that I can't control the I/O buffer.  The I/O pin acts as if it is always in tri-state.  I can read back my control registers and I've verified that the correct bits are being written.  My working assumption is that the T input to the OBUFT is not working correctly.

 

     I've saved off a copy of a working version of the FPGA (with Chipscope Inserter code).  Using planAhead I found the location of the register bit that control the OBUFT.  I've created some constraints that LOC'd those registers in the 'working'  location.  I'm feeding these constraints into a non-Chipscope version.  We'll see how this works out.

 

     Marv

 

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Registered: ‎02-25-2008


@marvinscheinbart wrote:

     What I mean by not working is that I can't control the I/O buffer.  The I/O pin acts as if it is always in tri-state.  I can read back my control registers and I've verified that the correct bits are being written.  My working assumption is that the T input to the OBUFT is not working correctly.

 


I wonder if something is being optimized away. check the synthesis reports.

----------------------------Yes, I do this for a living.
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Registered: ‎05-09-2014

     The problem has been resolved by performing a project cleanup.  My guess is that some files were not being updated like I expected.  Cleaning out all the old files and regenerating everything did the trick.

 

      Marv

 

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