05-01-2012 08:44 AM
My project uses virtex 6 XC6VLX760. The LUT utilization from synthesis report (synplify_premier) is around 70%. In most cases it couldn't be succssfully routed. I have seen the least 3 signals are not completely route, the most, like 199081 signals are not completely routed. Sometimes ISE spends 22 hours, sometimes 5 hours and then reports it can't finish the job.
There are a lot of timing violations which we are working on to clean up.
My question is if it's common that ISE can't finish the job if the utiliaztion is around 70%? Is there any way to improve it? like timing clean up?
05-01-2012 09:09 AM
Try a slower set of global clock constraints. See if it completes with lower constraints.
It may very well be that your clock frequency is too aggressive, not the number of LUT.
05-01-2012 09:29 AM
If the clock is only 40 MHz, that suggests that you have far too many levels of logic in your design. I would examine where you have such huge delays from many levels of logic, and figure out how to re-architect it to reduce the number of levels of logic between registers.
This sounds like RTL (verilog or VHDL) that was written for an ASIC that is now targeted for a FPGA device. In an ASIC, many levels of logic might have a very small delay, while in a FPGA device, every level of logic requires interconnect. And, the RTL may not be making use of DSP, BRAM, and other hardened blocks that would be very efficent (and much faster).
To achieve high speeds, one has to limit the number of levels of logic between registers to a small number, like no more than 3 LUT cascaded.
05-01-2012 09:51 AM
Thanks. Yes, you are right, the RTL is originally written for ASIC.
So what you mean is the number of levels would cause huge delays (I understand this) and then would affect the ISE to finish the routing.
05-02-2012 01:52 AM