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Observer
Observer
4,430 Views
Registered: ‎05-24-2011

PCIE v2.3 coregen does not give pin numbers in ucf

 
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Observer
Observer
4,423 Views
Registered: ‎05-24-2011

 
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Teacher
Teacher
4,417 Views
Registered: ‎09-09-2010

So, solved or not?

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"If it don't work in simulation, it won't work on the board."
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Observer
Observer
4,409 Views
Registered: ‎05-24-2011

Not solved.  I still do not know which pins to connect the reference clock to.  There are two pair choices MGTREFCLK1P_113/MGTREFCLK1N_113  or MGTREFCLK0P_113/MGTREFCLK0N_113. 

 

If there is a document somewhere that translates what I see in the ucf to actual pin numbers that would be great.

 

Anyone know why my text does not show up in the post?  The "wrong forum" tag may have something to do with it.  It would be helpful to let me know what the correct  forum is.

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Teacher
Teacher
4,404 Views
Registered: ‎09-09-2010

Probably the Packaging and Pinout Specification for whichever family of FPGAs you are using. For Virtex-5 it is UG195.

There is a PCIe-specific forum:
http://forums.xilinx.com/t5/PCI-Express/bd-p/PCIe

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"If it don't work in simulation, it won't work on the board."
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