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Observer wcdtom
Observer
8,085 Views
Registered: ‎09-30-2014

PLL on Virtex-5

  Hello, I am trying to realize SFI interface using the code in XAPP856. The system need two clock source (200MHz and 625MHz), but my PCB only has one clock source (125MHz). I want to use PLL to generate the other two clock source.

 

  The following code shows the method I try to use:

 

clk_200 clk_200
                (
                 .CLKIN1_IN(CLK_125B),
                 .RST_IN(RESET),
                 .CLKOUT0_OUT(CLK200),
                 .CLKOUT1_OUT(CLK_125)
                 );
      
clk_625  clk_625
               (
               .CLKIN1_IN(CLK_125),
               .CLKOUT0_OUT(CLKOUT_TX),
               .CLKOUT1_OUT(TXCLKDIV_W),
               .RST_IN(RESET)
               );

 

  Above, clk_200 and clk_625 are the PLL I set. When translate, there are following errors reported:

  

ERROR:NgdBuild:770 - IBUFG 'clk_625/CLKIN1_IBUFG_INST' and BUFG
   'clk_200/CLKOUT1_BUFG_INST' on net 'CLK_125_W' are lined up in series.
   Buffers of the same direction cannot be placed in series.
ERROR:NgdBuild:924 - input pad net 'CLK_125_W' is driving non-buffer primitives:

 

Can these problems be solved? How to solve it.

 

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1 Reply
Moderator
Moderator
8,035 Views
Registered: ‎02-16-2010

Re: PLL on Virtex-5

If you are connecting the output of one pll to the second, you will need to remove the IBUFG instantiation in the second PLL module.

Please remove the IBUFG in clk_625 instance of the PLL and connect input net to the IBUFG to output net.
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