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Visitor xfried00
Registered: ‎07-08-2008

PMA PLL issue on the GTX transceiver



I'm trying to implement XAUI on the Virtex5 TX150T using Xilinx XAUI core v9.1. There is a number of XAUI interfaces on our board, some of them are connected to transceivers on the left side of the FPGA, some to the right. Clocking is done by 156.25MHz oscillators connected to MGT's dedicated clock pins and I checked by scope that all clock sources are OK. On the right side of the FPGA (even numbered MGTs), all transceivers are working fine. But on the left side, PLLs inside GTX_DUALs do not generate clocks (REFCLKOUT does not toggle).
I also tried Gigabit Ethernet setup for MGTs, generated by the RocketIO GTX Wizard. Clocking was done by the GREFCLK, but the behaviour was exactly the same - the transceiver worked when it was locked to the right side of the FPGA, and it didn't work on the left side.

Does anybody faced such a problem? Is there any parameter that affects MGT operation on the left or right side? Thanks for any suggestions.


Best regards,


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Xilinx Employee
Xilinx Employee
Registered: ‎01-03-2008

Re: PMA PLL issue on the GTX transceiver

There shouldn't be any difference between the left side and right side implementations.  Not getting a REFCLKOUT from the MGT indicates that this is a major failure.


I would suggest the following:


1) Double check the UCF locations of the REFCLK and MGTs against your schematic

2) Verify that the correct power levels are present on the left side MGTs both on the board and in your schematic

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Xilinx Employee
Xilinx Employee
Registered: ‎08-06-2007

Re: PMA PLL issue on the GTX transceiver

Is the reference clock coming into one of the GTXs that is instantiated in the design?  If it's not and you need the clock to route through other transceivers, you will need to make sure that they are instantiated and powered correctly.  Nothing has to be done with these instances and they can be powered down for the most part, keeping REFCLKPWRDNB tied high.  The GTX user's guide has instructions for how each tile needs to be powered when used for routing a clock.



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