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Explorer
Explorer
8,341 Views
Registered: ‎05-21-2009

Partial reconfiguration in VHDL

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Good day Guys,

Can someone please help me? I'm trying to implement my own partial reconfigurable design after working through the PlanAhead tutorial. However, there is something not quite clear to me regarding the VHDL design of the appliation. While implementing my own design, I don't have any "undefined instances" in PlanAhead. This tells me that I am doing something wrong in implementing the components in VHDL. I've tried looking at the reference design code, but I can't seem to find anything done differently. It might be because the design is in Verilog (which I'm not really familiar with). How should I implement the components in VHDL so that PlanAhead treats them as undefined instances?

Thanks in advance!
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Adventurer
Adventurer
10,249 Views
Registered: ‎01-13-2011

Re: Partial reconfiguration in VHDL

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Hi,

 

In fact, all reconfigurable modules must have the same entity name and the same ports. So basically, you instanciate your reconfigurable component as a black box which has a "generic" port map of your reconfigurable modules.

 

Your first method was wrong because you comment and uncomment the component and the software can't see the black box in which you will put your reconfigurable modules.

 

As you understood, you make the synthesis of the top_fpga which instanciate the blackbox (if you run synthesis with XST go in the synthesis options and choose keep hierarchy, this is important) and you create a new project for all reconfigurable modules (for all reconfigurable modules, don't forget to disable buffer insertion).

 

In PlanAhead, you first import the netlist top_fpga containing the blackbox and its UCF file. After that, you can go in the netlist hierarchy and you will see your blackbox. This blackbox can be declared as a reconfigurable partition and you will be able to import your modules in it. This is well documented in the tutorials i think. If you have problem, do not hesitate.

 

Lamonnis

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6 Replies
Adventurer
Adventurer
8,332 Views
Registered: ‎01-13-2011

Re: Partial reconfiguration in VHDL

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Hello,

 

The undefined instance is the reconfigurable component that you must declare in blackbox. When you run synthesis on your top_fpga, remove all files that are in your reconfigurable partition, the black box replace all these components. After that, create another new project and run synthesis on your reconfigurable module. You have now 2 ngc or edif files.

 

Run planAhead and load your netlist top_fpga with its ucf file. After that PlanAhead must detect your undefined instance declared as a black_box.

 

Hope this help

 

Lamonnis

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Explorer
Explorer
8,322 Views
Registered: ‎05-21-2009

Re: Partial reconfiguration in VHDL

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Hi Lamonnis,

 

Thanks for the reply.

 

Am I understanding this correctly, I declare the reconfigurable components in the top level (as components), but should leave the port mapping out? Then I create a new project for each of the reconfigurable entities as if they were stand-alone applications. I then perform synthesis on each of them and I use the netlists in PlanAhead?

 

My current method is basically: I have a top level design with the reconfigurable components declared and instantiated. I then comment the reconfigurable components out and synthesize to get a top level netlist. Then gradually uncomment the reconfigurable modules to get netlists of the various configs. I'm guessing I understood incorrectly from the tutorial?

 

@ the moderators: sorry for posting in the wrong section. Didn't realize I was in the wrong section. I was under the impression I changed sections before posting.

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Adventurer
Adventurer
10,250 Views
Registered: ‎01-13-2011

Re: Partial reconfiguration in VHDL

Jump to solution

Hi,

 

In fact, all reconfigurable modules must have the same entity name and the same ports. So basically, you instanciate your reconfigurable component as a black box which has a "generic" port map of your reconfigurable modules.

 

Your first method was wrong because you comment and uncomment the component and the software can't see the black box in which you will put your reconfigurable modules.

 

As you understood, you make the synthesis of the top_fpga which instanciate the blackbox (if you run synthesis with XST go in the synthesis options and choose keep hierarchy, this is important) and you create a new project for all reconfigurable modules (for all reconfigurable modules, don't forget to disable buffer insertion).

 

In PlanAhead, you first import the netlist top_fpga containing the blackbox and its UCF file. After that, you can go in the netlist hierarchy and you will see your blackbox. This blackbox can be declared as a reconfigurable partition and you will be able to import your modules in it. This is well documented in the tutorials i think. If you have problem, do not hesitate.

 

Lamonnis

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Explorer
Explorer
8,300 Views
Registered: ‎05-21-2009

Re: Partial reconfiguration in VHDL

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Hi Lamonnis,

 

Thanks for your help. I'm gradually on my way to get my partial reconfiguration application running. PlanAhead is detecting my reconfigurable module, but when I try to generate the bitstreams, it fails. It tells me that my clock is unrouted. Now, I'm guessing it has something to do with the I/O buffering. Could you explain a couple of concepts for me, which is not quite clear?

 

You said I should keep the hierarchy. It seems that it keeps the synthesis from "flattening the design". What is implied by this and why is is relevant to reconfiguration? Why should I/O buffering be disabled?

 

Am I understanding this correctly: The hierarchy should be kept throughout the design, but I/O buffering should only be disabled when synthesizing the lower level modules, thus it should be enabled when synthesizing the top level?

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Adventurer
Adventurer
8,295 Views
Registered: ‎01-13-2011

Re: Partial reconfiguration in VHDL

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Hi,

 

You should keep hierarchy when you synthesize your top_fpga. That allows you to see your black box in sub-modules. Sorry, I am not native english/american so i don't undertand what you mean by flattening the design :). If you test whitout keeping hierarchy, you will see your top level module and not submodules. As consequence, you will not be able to select your black box as a reconfigurable partition. I cannot remember where I read that I/O buffer must be disable, but that is clear (in UG702) is that BUFG are forbiden.

 

As a summary, for top _fpga, just put keep hierarchy, for submodules, just remove buffer insertion, you have well understood :)

 

 

 

 

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Explorer
Explorer
8,292 Views
Registered: ‎05-21-2009

Re: Partial reconfiguration in VHDL

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Hi,

 

Thank you very much for all your help. The application is working perfectly.

 

I guess what is meant by "flattening the design" (I got the term from Xilinx's documents) is that the synthesizer interprets modules instantiated into other modules as a single module. I could be wrong though. Nevertheless, my design is working. Thanks for your support.

 

Kind regards

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