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Visitor
Visitor
11,049 Views
Registered: ‎12-12-2013

Phase differences between TX/RXUSRCLKs within a V6 GTH QUAD

The TX and RX USRCLKs can be shared between transceivers within the same QUAD under certain circumstances.

 

My question however is, are the 4 different TX and RX USRCLK outputs all exactly the same, or are there phase differences between them?

 

Each lane seems to have a different Tx and Rx fabric clock divider, but all sourced from the same PLL, so not sure about this one actually. It doesn't really mention anything about this in documentation.

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Xilinx Employee
Xilinx Employee
11,038 Views
Registered: ‎07-31-2012

Re: Phase differences between TX/RXUSRCLKs within a V6 GTH QUAD

Hi cheyert,

 

I think you should expect minor phase differences due to the path difference travelled by the CLOCK input to the different quad's and also if there are any setting difference between the quad's. However i guess you are looking for multlane appliications.

 

However if you are looking for Multilane applications check below

 

TX Multilane can be found from Pg 90 of UG371LINK

 

Configuring the Transmitter for Multi-lane Applications
The GTHX4LANE port in GTH transceivers is used for multi-lane applications that require
minimum skew across channels. To configure four GTH lanes within a Quad into a single
x4 link, GTHX4LANE must be tied High. When configured in a single x4 link, a change in
the control settings on the master lane also causes the same effect on the slaves. An
exception to this is the POWERDOWN port. In this x4 link configuration, the buffers across
the four transmit data converter are synchronized for minimizing skew.

 

RX Multilane can be found from Pg 147 of UG371 

 

To configure four GTH lanes within a Quad into a single x4 link, the GTHX4LANE port
must be tied High. When configured in a single x4 link, a change in the control settings on
the master lane also causes the same effect on the slaves, except with the POWERDOWN
ports. The POWERDOWN ports of all GTH lanes within a Quad in a x4 link should be
driven by the same source.

 

 

Thanks,
Anirudh

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Xilinx Employee
Xilinx Employee
11,035 Views
Registered: ‎01-03-2008

Re: Phase differences between TX/RXUSRCLKs within a V6 GTH QUAD

The TX/RXUSRCLKs are the digital domain clocks for te TX/RX data paths. The TXDATA will setup time to the TXUSRCLK2 and the RXDATA will have a cook-to-out relative to RXUSRCLK2 and this will be correctly time to the fabric registers. Any minor clock skew differences will be counted for by the timing analyzer.
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Xilinx Employee
Xilinx Employee
11,006 Views
Registered: ‎07-31-2012

Re: Phase differences between TX/RXUSRCLKs within a V6 GTH QUAD

Hi Cheyert,

 

Is your query resolved? Lets us know if you need any further help.

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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