06-02-2014 10:17 AM
I have a board that has the XQ5VLX220T and the XQ5VFX130T FPGA’s on it. I have a situation where there has been some ±2V ringing on the 3.3v lines. The duration of the pulse is 30us. I am trying to determine if the FPGA’s have been damaged. Any help, thoughts, suggestions would be appreciated.
06-02-2014 10:40 AM
If you exceeded the absolute maximum ratinmgs in Table 1, then all bets are off (damage has very probably occurred which will lead to immediate failure, or a sooner than expected failure).
+/- 2.0 volts at the silicon itself is entirely unlikely, however. If that was the voltage at the IO pin, the voltage at the die itself is clamped by the intrinsic body diodes of the output nmos and pmos stacks to about a diode drop.
Measuring the voltage at the pin of the package with as short as possible loop for the signal and the ground (less than 1mm for each) is non-trivial (usually requires a very special high speed, low inductance probe setup).
Injecting more than 200 mA on all IO's, or more than 100 mA on a bank may cause IO latchup, and immediate failure.
Given that did not happen, I would simulate the IO (using the IBIS models, and your PCB traces and connected loads) and see EXACTLY what the internal IO at the die is doing, in both current, and voltage.
It may be you have no problem at all (beside a lousy signal intergity situation which may lead to data errors or other problems, but results in no damage to the device).
06-02-2014 03:27 PM
Thanks for the quick response. The ripple was on the power supply line was measured at the power supply. It was not on the I/O lines. If that helps. I noticed a power-on/off power supply sequencing calculation for the Vertex-7. It there an equivalent for the Vertix-5's?
06-03-2014 07:19 AM
Yes, the preferred sequence is in the data sheet. Using a non-preferred sequence may result in IO pins glitching while powering ON. The suggested sequence precludes that happening.