04-26-2011 07:04 AM
I am using Virtex-II (XC2V250-4CS144) FPGA and 4Mbit Xilinx Platform flash (XCF04S). I am facing problem in configuring and programming FPGA.
Around 30 boards were built with the above mentioned FPGA and flash and tested sucessfully without any problem. After that I changed the value & size of some components (capacitors) of our board,s analog part. Now I got new PCB with modifications in the layout related to analog part only (FPGA related layout not changed and it is verified).
With the new PCB I faced the following problems:
1. Even though there are 2 devices (Flash and FPGA) in chain, JTAG is detecting only FPGA.
2. I have an option to modify the JTAG chain. This time I made the hardware such that there is only flash in the JTAG chain. Now JTAG detected the flash and it is programmed without any problem.
Here the problem is FPGA is not generating CCLK and it is not configuring in power on state as well as with LOW going pulse on PROG_B .
3. I did 1 more modification in hardware. Now I have only FPGA in JTAG chain. This time also JTAG detected FPGA. But the problem is when I want to read IDCODE or I want to program FPGA with a bit file it is not happening. Expected and actual IDCODEs are not matching.
4. When a LOW signal applied to PROG_B pin I am not seeing a LOW going signal on INIT_B.
5. Finally I used ENABLE/DISABLE DEBUG CHAIN feature of iMPACT tool. With this I verified IDCODE. I got proper IDCODE.
I am using Xilinx USB-II cable with TCK speed of 750KHz. I verified it with 6MHz speed also.
Please suggest me to solve this problem.
Thanks in advance.
04-26-2011 08:58 AM
The first place I'd look is at the power supply voltage levels to the FPGA. Check the
configuration user guide to be sure which ones are actually used for configuration.
I don't remember about Virtex 2, but some other families require one or more
banks' Vcco for configuration as well as Vccint and Vccaux.
In the first case of JTAG with both devices in the chain and only detecting the FPGA,
then I would suspect the chain where the flash TDO connects to FPGA TDI.
Other than that, you might really double check that the layout matches the
original layout for the FPGA part.
04-26-2011 11:07 PM