02-02-2012 03:44 AM
I am using Virtex 4 FPGA. In partial reconfiguration User guide it says that ICAP OUTPUT can be used to monitor the status of configuration. In my design, while i'm loading partial bitstream, i read ICAP output port bit 7. But this bit is always 0. After a power on full configuration and after a partial reconfiguration. But if i see init pin it is high, indicating a successfull configuration. I tried to read other bits of icap output (bit 6, bit5, bit4) but they are always low.
02-06-2012 08:46 AM
Please refer to http://www.xilinx.com/support/answers/8520.htm and remember byte-swap nature. If you're getting all '0' out of the ICAP output, you should double check to ensure you're not accessing the idle ICAP (bottom). You can check your ncd file via FPGA_EDITOR.
02-06-2012 11:19 AM
Thanks for your reply.
I've checked with FPGA editor that i read the output of the correct ICAP;
Something strange happens..if i do an abort and wait four clock cycles the output change from 0x00000000 to 0x0000009F, that is correct...but why i need to do first an abort sequence?
I also tried to read ouput after write a wrong bitstream and bit7 goes to 0 signaling a configuration error, then write a correct bitstream and bit 7 goes to 1...so it is correct...but if i do not first an abort, icap output remains always 0x00000000.
02-06-2012 11:59 AM
Interesting. Do you have a running ICAP clock? Can you double check to make sure you didn't "persist". That should be in your .bgn file.
You shouldn't need to do abort. It's been a while since I've played with V4 ICAP, but I don't recall this particular issue. I know V5/6/7-series definitely do not have this. Maybe worth a while to send your bitstream and bgn file to the Xilinx tech support to see if any config register bit got set incorrectly.
02-06-2012 12:22 PM
02-06-2012 12:28 PM
You're right. It should wake up to 9F. Here's a chipscope shot for a V6 project that I've done. It's the same for 7-series and also V5. I didn't see any problem with your bgn. Is your clock slower than 50MHz? Can you try 25MHz or slower? If you have another board, I'll recommend giving that a shot as well.
02-06-2012 12:43 PM
My clock is about 65 Mhz...why i should try with a clock lower than 50 MHz? I tried icap up to 100 Mhz and configuration was fine. I tried yet with chipscope to observe icap bit 7 and after startup it is '0'. It is like that to activate the icap output i must do an abort sequence. Then it functions correctly..it is not a severe problems in my design, but it differs from user guide.
Thank you for your suggestions.
02-06-2012 12:56 PM
You're right. Max config for ICAP is 100MHz. Max readback is slower. One other thing that may worth checking. See if you've reached end of startup after config. You can get the EOS bit with iMPACT's debug -> Status Registers.
02-07-2012 12:53 AM - edited 02-07-2012 03:15 AM
I checked status register with impact and result is:
CRC error : 0
Decryptor security set : 0
DCM locked : 1
DCI matched : 1
End of startup signal from Startup block :1
status of GTS_CFG_B : 1
status of GWE : 1
status of GHIGH : 1
value of MODE pin M0 : 1
value of MODE pin M1 : 1
Value of MODE pin M2 : 0
Internal signal indicates when housecleaning is completed : 1
Value driver in from INIT pad : 1
Internal signal indicates that chip is configured : 1
Value of DONE pin : 1
Indicates when ID value written does not match chip ID : 0
Decryptor error Signal : 0
System Monitor Over-Temperature Alarm : 0
11-15-2013 05:29 AM
I tried with another Virtex 4 device (VLX100) and the problem is the same.
It seems that in Virtex4 devices at startup the ICAP output bit 7 is '0'.
It goes to '1' only after the first partial reconfiguration or the first abort sequence. Then it behaves normally for all subsequent operations.