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Scholar samcossais
Scholar
8,406 Views
Registered: ‎12-07-2009

Problem with MIG when STARTUP_VIRTEX6 is instantiated

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Hi,

 

My DDR2 interface doesn't work when I intantiate the STARTUP_VIRTEX6 primitive.

 

I am working with a Virtex-6 using ISE13.1. My design includes a DDR2 interface for which I use MIG v3.7

I use STARTUP_VIRTEX6 for post configuration SPI ROM access. All unused inputs including GSR are left unconnected.

 

I searched for the origin of the problem in simulation waveforms and I found that GSR is slightly different when instantiating STARTUP_VIRTEX6, finally causing the MIG initialization to fail. Only disabling STARTUP_VIRTEX6 makes MIG work properly.

 

I check that this behavior is true for both simulation and hardware test.

 

My question is :

how should I connect STARTUP_VIRTEX6 GSR input to be sure STARTUP_VIRTEX6 won't have any influence on my FPGA startup sequence ?

 

Thanks in advance for your help !

Regards,

Sam

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Accepted Solutions
Scholar samcossais
Scholar
11,226 Views
Registered: ‎12-07-2009

Re: Problem with MIG when STARTUP_VIRTEX6 is instantiated

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GSR=0 did work in hardware ! MIG initialization passed. Thank you very much for your help !

 

To be precise, the following code :

 

`ifdef SIMULATION
   assign my_gsr = glbl.GSR_int;
   assign my_gts = glbl.GTS_int;
`else
   assign my_gsr = 1'b0;
   assign my_gts = 1'b0;
`endif

 

works in both simulation and hardware (0 works for hardware but not for sim).

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8 Replies
Advisor evgenis1
Advisor
8,390 Views
Registered: ‎12-03-2007

Re: Problem with MIG when STARTUP_VIRTEX6 is instantiated

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Hi,

 

Attached is a working example of STARTUP_VIRTEX6 connectivity. The design also uses post-configuration SPI Flash access. The design doesn't have DDR interface, so I cannot tell if there is a problem or not.

 

One thing is that STARTUP_VIRTEX6 has to be instantiated in the top level of the design. I've seen odd problems with black boxes and partitions if STARTUP_VIRTEX6 is not in the top level. That was also the workaround recommended by Xilinx when I opened the WebCase. You might want to give it a try.

 

 

Thanks,

Evgeni

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Scholar samcossais
Scholar
8,385 Views
Registered: ‎12-07-2009

Re: Problem with MIG when STARTUP_VIRTEX6 is instantiated

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Hi Evgeni,

 

Thank you very much for your kind reply. I checked your file. What value do you set for FALSE ?

Do you write it like this ?

localparam [0:0] FALSE = 1'b0;

If it is the case my MIG still doesn't work after doing it.

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Scholar samcossais
Scholar
8,384 Views
Registered: ‎12-07-2009

Re: Problem with MIG when STARTUP_VIRTEX6 is instantiated

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by the way my STARTUP_VIRTEX6 instance was alrealy inside the top level file.

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Advisor evgenis1
Advisor
8,376 Views
Registered: ‎12-03-2007

Re: Problem with MIG when STARTUP_VIRTEX6 is instantiated

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Yes, FALSE is 1'b0.

 

Can you provide more details on how the MIG fails. Is it kept at reset, or one of the training phases doesn't complete. Does it fail the same way when you run it on your hardware and in simulation.

 

 

Thanks,

Evgeni

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Scholar samcossais
Scholar
8,374 Views
Registered: ‎12-07-2009

Re: Problem with MIG when STARTUP_VIRTEX6 is instantiated

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Well my hardware test was very simple, I just checked init_done signal from MIG, which got asserted when STARTUP_VIRTEX6 was instantiated, and didnt when STARTUP_VIRTEX6 was not instantiated.

 

At this level I thus get the same result in hardware and Modelsim. Now as regards with simulation, I checked glbl instance in Modelsim and could see a difference in GSR behavior after reset whether STARTUP_VIRTEX6 is present with GSR input = 1'b0 or not. In the first case, GSR was never asserted (always 0), in the second case GSR was asserted first, then deasserted after 100ns.

 

After checking glbl and STARTUP_VIRTEX6 sources, in my opinion I would say the problem is that STARTUP_VIRTEX6 is making a default assignment (which is strong) for GSR, while glbl makes a weak assignment. Therefore STARTUP_VIRTEX6 GSR input will always override the default GSR behavior (that is 1 at startup and then 0 after 100ns).

 

In most of the cases this shouldn't be a problem but MIG reset sequence seems to be quite dependent on GSR behavior (it seems that at least it requires that GSR is once asserted and then deasserted).

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Scholar samcossais
Scholar
8,371 Views
Registered: ‎12-07-2009

Re: Problem with MIG when STARTUP_VIRTEX6 is instantiated

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I'm going to try this code in hardware:

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Scholar samcossais
Scholar
8,365 Views
Registered: ‎12-07-2009

Re: Problem with MIG when STARTUP_VIRTEX6 is instantiated

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Also when MIG fails, it is kept at reset (MIG reset is x).

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Scholar samcossais
Scholar
11,227 Views
Registered: ‎12-07-2009

Re: Problem with MIG when STARTUP_VIRTEX6 is instantiated

Jump to solution

GSR=0 did work in hardware ! MIG initialization passed. Thank you very much for your help !

 

To be precise, the following code :

 

`ifdef SIMULATION
   assign my_gsr = glbl.GSR_int;
   assign my_gts = glbl.GTS_int;
`else
   assign my_gsr = 1'b0;
   assign my_gts = 1'b0;
`endif

 

works in both simulation and hardware (0 works for hardware but not for sim).

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