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laurent_golay
Visitor
Visitor
5,719 Views
Registered: ‎03-05-2009

Problem with Virtex 5 configuration with SelectMap mode

hello,

First, sorry for my bad english.

I have got a board with a microprocessor, a CPLD and an FPGA Virtex-5 (XC5VSX50T).

My objectiv is to configure the FPGA with de processor within de CPLD by the Slave SelectMap mode.

The CPLD drive the configuration signals following your application note's indication

The first part of the configuration takes place correctly. I hold the PROGRAM_B pin low for about 350 ns. In response the FPGA drive the INIT_B signal down for about 750 us. According to your application note, the rise of the INIT signal sample mode pins.

In order to use the Non-Continuous Slave SelectMAP Data Loading with Controlled CCLK configuration mode, I assert CS_B and RDWR_B low.

According to your documentation, the BUSY pin should go low. But this is not the case. This signal stay high.

If I try anyway to configure the FPGA by sending CCLK and Data, the DONE pin never rise up.

I tried to use the Master SelectMap mode. In this mode, the BUSY pin is properly toggled low. Unfortunately the CCLK generate by the FPGA is too quick for my architecture.

The problem seems to come from this BUSY pin that didn't go down.


Thanks in advance
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2 Replies
erikhj
Visitor
Visitor
4,743 Views
Registered: ‎04-08-2010

Hello!

 

I understand that this thread is a little bit old but I have the same problem.

 

Perhaps someone has an answer this time or have you found a solution?

 

If you have, can you please tell me how.

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mcgett
Xilinx Employee
Xilinx Employee
4,739 Views
Registered: ‎01-03-2008

In the original poster's case the likely failure was that CCLK was not toggling at the beginning of the configuration.
------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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