I am using Xilinx ISE 10.1i web pack edition. My design requires that the IO standard of the pins coming in and out of FPGA should be of type LVCMOS 3.3 V. I used PACE feature of Xilinx ISE to assign the IO standard. But whenever my logic drives a high, the output pins only reach 2.5 volts max. But whenever an input signal which is 3.3 volts is taken into FPGA and brought out it has a proper voltage value. I have not used any service pack. Can someone please suggest me a solution to this problem.