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Visitor
Visitor
4,524 Views
Registered: ‎09-19-2008

Problem with constraining IO standard

Hi,

        I am using Xilinx ISE 10.1i web pack edition. My design requires that the IO standard of the pins coming in and out of FPGA should be of type LVCMOS 3.3 V.  I used PACE feature of Xilinx ISE to assign the IO standard. But whenever my logic drives a high, the output pins only reach 2.5 volts max. But whenever an input signal which is 3.3 volts is taken into FPGA and brought out it has a proper voltage value. I have not used any service pack. Can someone please suggest me a solution to this problem.

 

Thanks in advance

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Xilinx Employee
Xilinx Employee
4,516 Views
Registered: ‎08-13-2007

Re: Problem with constraining IO standard

You should likely be using service pack 3 for 10.1 (10.1.03);

http://www.xilinx.com/support/download/index.htm

But I wouldn't expect that to change this situation.

 

1) How did you measure the voltage (DVM, oscilloscope, etc.)?

2) Did you use the same I/O pin for the output in the 2 test cases?

3) What is the I/O voltage (Vcco) of the banks used for the outputs?

4) What is the load seen by the output, e.g. testpoint, another IC, pull-down resistor, some combination, etc.

 

The most common cause of this is using an output in a bank with a Vcco of 2.5V. The I/O standard of LVCMOS33 can't fix this.

 

bt

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