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Registered: ‎03-06-2014

Problem with sampling of the outputs of a CARRY4 delay line chain

Hello friends,
I would like to share my current issue with you and get your advise about it. I am working on a CARRY4 delay line based design in order to sample its output and in each clock rising edge, I would like to compare the sampled output with the old latched output by CARRY4 delay line chain.
I configured a delay line with CARRY4 primitives with 256 states that captures a digital signal called trigger coming from an LFSR (Linear Feedback Shift Register). At each rising clock transition of tdc_clock that is 400 MHz, I sample the captured signal by a DFlipFlop and compare it with its previous captured signal. As you see in the attached timing diagram, I provide the compared_output signal by subtracting the latched_output (captured by delay line) and thesampled_outout to detect any difference. A flag called ODC_result_sig will be raised if the comparison result is not 0.  But I do not know why my compared result is not always 0 because I did not inject any extra delay to the digital signal and ODC_result_sig is raised unnecessarily. Could you please verify my timing diagram and give me your idea to figure out the problem?
I also send you my architecture for sampling and comparison as well as the definitions of sampling circuit and its initialization and the comparison method in the following:
------------------ Sampling circuit with DFF -----------------
D => latched_output_sig,
Q => sampled_output_sig,
QN => open,
CLK => clock_400MHz_AND,
RESET =>  sync_reset
------------- writing a process for compared_output calculation -------
process (clock_400MHz_AND, latched_output_sig, sampled_output_sig) begin if(RISING_EDGE(clock_400MHz_AND)) then compared_output <= sampled_output_sig - latched_output_sig ; compared_output_1bit <= sampled_output_sig(255 downto 254) - latched_output_sig(255 downto 254); compared_output_first <= sampled_output_sig(15 downto 0) - latched_output_sig(15 downto 0); end if; end process; -----------------------------------------------------------------------
I thank in advance for your always kind consideration and assist.
pic 2 sampling architecture.jpg
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Registered: ‎08-14-2007

Re: Problem with sampling of the outputs of a CARRY4 delay line chain

It looks like the output of your TDC block is changing twice each time you get a trigger.  If this is expected, and you only want to compare the values after the trigger goes low, then you need to account for it in your delay and compare logic.

-- Gabor
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