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Observer arrubyyan
Observer
8,072 Views
Registered: ‎05-23-2014

Read First mode in 7 Series Distributed Rams

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Hi,

 

I know in the block ram generator IP we have this option to choose the mode, like read first or write first, I was wondering do we have the same flexibiilty in distribted ram? if not what is the default? if yes how can I use it?

 

Thanks,

Aryan

 

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Historian
Historian
15,731 Views
Registered: ‎01-23-2009

Re: Read First mode in 7 Series Distributed Rams

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The architecture of the distributed RAMs really don't bear any resemblance to the block RAMs...

 

They do not have any equivalent to the WRITE_MODE.

 

But its much more than that - the distributed RAMs have an asynchronous read - the read data is combinatorially generated based on the address. The writes, though, are still synchronous.

 

So, if you generate an address to the distributed RAM, the current contents of the RAM will appear with a small propagation delay. If you also assert the WE, then on the next rising edge of the clock, the contents of the RAM will be changed to the new value (and if you leave the address the same, the new data will show up shortly thereafter).

 

Therefore, if you were to put flip-flops on the outputs of the RAMs (which will give them a 1 cycle read latency, like the block RAMs), then the contents in the flip-flops after a write operation will correspond to the previous contents of the RAM - similar to the "READ_FIRST" mode of the block RAMs.

 

Avrum

2 Replies
Highlighted
Historian
Historian
15,732 Views
Registered: ‎01-23-2009

Re: Read First mode in 7 Series Distributed Rams

Jump to solution

The architecture of the distributed RAMs really don't bear any resemblance to the block RAMs...

 

They do not have any equivalent to the WRITE_MODE.

 

But its much more than that - the distributed RAMs have an asynchronous read - the read data is combinatorially generated based on the address. The writes, though, are still synchronous.

 

So, if you generate an address to the distributed RAM, the current contents of the RAM will appear with a small propagation delay. If you also assert the WE, then on the next rising edge of the clock, the contents of the RAM will be changed to the new value (and if you leave the address the same, the new data will show up shortly thereafter).

 

Therefore, if you were to put flip-flops on the outputs of the RAMs (which will give them a 1 cycle read latency, like the block RAMs), then the contents in the flip-flops after a write operation will correspond to the previous contents of the RAM - similar to the "READ_FIRST" mode of the block RAMs.

 

Avrum

Observer arrubyyan
Observer
8,061 Views
Registered: ‎05-23-2014

Re: Read First mode in 7 Series Distributed Rams

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Fair enough! thanks

 

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