04-06-2010 08:47 AM
I have created a ROM core using CoreGen to store a large chunk of data (65536 data values). When i instantiate the ROM in my main code, and when i give some address as input, i get the corresponding data value at the output port. So i'm sure the data is stored correctly in the ROM.
But how do i scan through the ROM? How do i access a chunk of data at a time, and not just one data value? I tried using the 'for' loop by storing data in an array, but the value stored at the last address indicated by the 'for' loop gets overwritten in all other places.
How do i access a big part of the ROM at a time?
I dint mean to mark it as "Solved"!!!
I have been trying to increment the address, but i keep getting the error -- Multiple declarations of "+" included via multiple use clauses; none are made directly visible -- wherever i use the '+' sign to increment the address.
What could be the reason??
04-06-2010 10:03 AM
What are you writing this in? VHDL/verilog, or c code?
Do you understand the difference between a hardware description language, and a software program?
When you describe something in a hardware description language, you are executing ALL statements, ALL at once, on each clock...this is the advantage of a hardware description language.
If you wish to sequenctially execute (like a c program) one statement at a time, one statement on one clock cycle, and then another statement on the next clock cylce, you can do that, by the coding style (see sequential processing vs. structual or behavioral coding of an architecture, component, or logic function).
So, as an example, if you are specifying hardware, a FOR n loop will make n copies of the hardware, so it can all execxute on one clock cycle. If you are specifying a sequencial operation, then a FOR n loop will execute once for each clock, with each statement processed one after the other (like a conventional software program) taking n cycles to complete.
The advantage of using the FPGA is that you can do everything, all at once. If you wanted a microprocessor, you should have used one.
A good rule to follow is one used by Peter Alfke many times: "if you can do it with a microprocessor, then do it that way" do not bother to use a FPGA device unless you need the capabiltiy, or flexibility...
If you are learning how to use a FPGA device, it is not a processor, so do not think of it like that, expand your mind: you can do everything, all at once (every line of the HDL code can be 'execute' on one clock edge). If you do not want everything to execute all at once, then you have to code in a way that tells thesynthesis tool want it is that you want...
04-06-2010 10:26 AM
Thanks for replying. I am writing a vhdl code.
I have figured out how to increment the address at every clock cycle. I just used a temporary variable in the clock process and after assignment of every address i incremented the temp variable.
Now i have to pass this ROM data through a filter. Im using a core FIR filter and i have loaded the coefficients and other parameters.
I suppose i can do this filteration too in the clock process isnt it?
But i don't understand the use of the "coef_din" input. Arent the coefficients already loaded in the *.coe file? And "coef_din" is not an array, so how do i load all these coefficients at 1 time?
04-06-2010 10:35 AM
Just so. The coefficients are all needed, at every clock cycle, so the coefficents must all be in static registers or on wires as constants. A ROM is the wrong place to put the coefficents.
A better place to put the coeficients is in constants, which will be implemented as wires to a 1, or a 0, as required, along with any logic required.
The data itself that needs to go through the filter can be in any form: in a ROM, a RAM, or coming into a input port (from a A/D converter, for example).
If the goal is to provide a filter with programmable coeficients, then the coeficients need to be in registers, and those registers need to be accessible to something (a microprocessor? state machine?) to vary as required. A ROM is a poor place to put the coefficients, as they will have to be read out, placed in parallel registers, connected to the coeficient bits of the filter...
If the coeficients do not need to change, then making these constants is the least expensive, they are reduced to wires to 1 and 0. No ROM needed at all.
04-06-2010 11:01 AM
I am designing a filter with 5 coefficients. And no, they arent programmable, they are constants. But isn't "coef_din" just 1-vector input (std_logic_vector(15 downto 0) say)? Can it be an array of constants? How do i feed "coef_din" with all 5 coefficients in one clock cycle?
04-06-2010 11:05 AM
Yes, the coeficients can all be constants. As wide, and as many as you need.