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Observer zubinkumar
Observer
8,993 Views
Registered: ‎11-23-2010

Reg: FD based shift regs for Virtex4 FPGA

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Hi,

 

I have an old design that uses an FD based shift register. The design was for spartan 2 FPGA but I want to run the same design on a Virtex4. Since FD based shift regs have been discontinued, how can I implement something similar for the V4? Can some IP core from coregen be used for this? I am using ISE 11.1 ...

 

Any inputs will be highly appreciated.

 

Thanks,

Zubin.

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1 Solution

Accepted Solutions
Instructor
Instructor
11,618 Views
Registered: ‎08-14-2007

Re: Reg: FD based shift regs for Virtex4 FPGA

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I'm having a bit of trouble understanding you here.

 

"Because the FD based shift reg. is not acting like a regular reg. "

 

Are you saying that the Coregen core doesn't behave like a normal D flip-flop?

 

Did your original core have asynchronous data load?

 

There are some differences in the logic cells for newer parts from the old Virtex

and Spartan 2 series.  I believe the older parts had the ability to have both async.

set and async. reset in the same flip-flop.  This made an easy path to do an asynchronous

load to a register.  The newer parts have only one async. input to the cell, which can

either be a set or reset but not both.  So you may need to work around the issue

by using a synchronous load and possibly a gate on the output to pass through

the input to the output whiloe the load signal is active.  It would not be exactly

the same as the original design unless the load signal was active for at least one clock period

to ensure the data was clocked into the registers.  Do you have the .xco file from

the old Spartan 2 cores?  I've attached a copy of the FD-based Shift register v 5.0

core data sheet.  It lists the parameters for the core as they should appear in

the .xco file.  You could possibly get some insight into what features were used

in the original core and how to achieve the same functionality.

 

HTH,

Gabor

-- Gabor
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7 Replies
Instructor
Instructor
8,992 Views
Registered: ‎08-14-2007

Re: Reg: FD based shift regs for Virtex4 FPGA

Jump to solution

While the older library primitives are no longer in the Libraries Guide for newer

architecture, I believe you can still use them, i.e. the library elements still exist.

 

What method of design entry do you use?  VHDL?  Verilog?  Schematics?

-- Gabor
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Observer zubinkumar
Observer
8,981 Views
Registered: ‎11-23-2010

Re: Reg: FD based shift regs for Virtex4 FPGA

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Hi,

 

Thanks for your reply!

 

I tried to use it, but ISE 11.1 throws an error (while implementation) that says the architecture of the FD based shift reg. is not supported on V4. The website says the core was discontinued after 5.1. I am using VHDL as the design entry method. 

 

I am guessing that FD based shift reg. cannot be implemented on V4. So is there some equivalent for it in ISE 11.1? Also, if I want to implement a bitwise shift reg. using ISE 11.1 on V4, what can I use that would come close to emulating the functionality of the FD based shift reg. on V4 hardware?

 

Thanks,

Zubin.

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Instructor
Instructor
8,979 Views
Registered: ‎08-14-2007

Re: Reg: FD based shift regs for Virtex4 FPGA

Jump to solution

O.K., I didn't realize you were talking about a Coregen core.  The really simple cores

like shift registers, counters, adders, etc.  were mostly removed from newer versions

of Coregen because inferring these structures directly from VHDL is at least as efficient

as using the core.  I don't know how many of these you have in your design, but if it

isn't too many I would suggest coding the shift registers directly where you would have

instantiated the cores.  If your design uses a lot of these cores, you might be better off

just coding a separate shift register in VHDL and instantiating that.  If you still have

the old version of ISE where you buit the cores, you can try to find the simulation models

for them to get an idea of how they work and make sure that your VHDL version

matches the functionality.

 

Regards,

Gabor

-- Gabor
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Observer zubinkumar
Observer
8,974 Views
Registered: ‎11-23-2010

Re: Reg: FD based shift regs for Virtex4 FPGA

Jump to solution

OK, 

 

You see coding it in VHDL seems to be the issue. Because the FD based shift reg. is not acting like a regular reg. Especially in one particular case where a new value is loaded into the reg. In that case the new value is loaded and the 0th bit of the previous input is displayed on the output line as well. Doing both ops in 1 stage creates a timing conflict while implementation on hardware and if I do it in separate stages, the entire functionality gets delayed by 1 clock cycle leading to garbled outputs. Moreover, the output of the FD based shift reg. coregen core comes after exactly 1 ns on the output line, which is hard to emulate when you're using a 100MHz sync. design in vhdl.

 

Any inputs on this ?

 

Thnx!

Zubin.

 

 

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Instructor
Instructor
11,619 Views
Registered: ‎08-14-2007

Re: Reg: FD based shift regs for Virtex4 FPGA

Jump to solution

I'm having a bit of trouble understanding you here.

 

"Because the FD based shift reg. is not acting like a regular reg. "

 

Are you saying that the Coregen core doesn't behave like a normal D flip-flop?

 

Did your original core have asynchronous data load?

 

There are some differences in the logic cells for newer parts from the old Virtex

and Spartan 2 series.  I believe the older parts had the ability to have both async.

set and async. reset in the same flip-flop.  This made an easy path to do an asynchronous

load to a register.  The newer parts have only one async. input to the cell, which can

either be a set or reset but not both.  So you may need to work around the issue

by using a synchronous load and possibly a gate on the output to pass through

the input to the output whiloe the load signal is active.  It would not be exactly

the same as the original design unless the load signal was active for at least one clock period

to ensure the data was clocked into the registers.  Do you have the .xco file from

the old Spartan 2 cores?  I've attached a copy of the FD-based Shift register v 5.0

core data sheet.  It lists the parameters for the core as they should appear in

the .xco file.  You could possibly get some insight into what features were used

in the original core and how to achieve the same functionality.

 

HTH,

Gabor

-- Gabor
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Newbie scsia16
Newbie
7,952 Views
Registered: ‎03-06-2014

Re: Reg: FD based shift regs for Virtex4 FPGA

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Hello guys,

 

I need help here. I have a very leagcy project targets on Virtex II that has this FD-based Shift Register V5.0 IP in my schematics top level project. Now in ISE 14.7, it couldn't find this component/IP anymore because it's being removed in this newer version. Would please suggest what is the workaround to replace this component/IP? My design is in schematic entry.

 

Thanks!!

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Newbie scsia16
Newbie
7,945 Views
Registered: ‎03-06-2014

Re: Reg: FD based shift regs for Virtex4 FPGA

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Wondering if I can edit the original symbol named SR16CE in Spartan 6 primitive by changing it parameter, says the parallel data output from original 16bits (as the name SR16CE indicates) to 8bits and reuse in my new schematic design? 

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