08-25-2009 12:33 PM
Xilinx's PR tools for ISE
9.2_pr have helped me create Partially Reconfigurable Regions (PRRs),
and swap Reconfigurable Modules (RMs) in and out of those regions (for Virtex4). The
partial bitstreams that are used to change the modules work fine. However, if the previous RM used
registers (flip-flops or latches) in the region, and the RM that is
being partially reconfigured over that region uses the same registers,
the registers are not re-initialized upon reconfiguration. So, when I
swap a module in, it will essentially start up in an unknown state,
depending on the last module state values.
I experimented with the CAPTURE_VIRTEX4 and STARTUP_VIRTEX4 primitives to reinitialize the flip-flop values, but it seems they only work globally for the entire chip. I am at a loss if there is any way to reinitialize the state register values for only part of the chip (without adding the set/reset line in the slice). I know the initialization values are getting written to the configuration plane, but is there a way to have just part of the chip (the PRR) reinitialize registers when it is partially reconfigured? I can not find any option in planAhead that enables me to do this.
Thank you for any help on this issue,
09-02-2009 10:15 AM
In correspondence with Xilinx Tech Support, they advise that Reconfigurable Modules (RMs) have reset capability built in to reset the flip-flops and state right after Partial Reconfiguration. However, this would neccesitate using all of the flip-flops SR lines, and adding logic to AND my own reset signal to the Reconfiguration reset signal. Of course this can be done, however, it seems to me that since the FPGA is reconfigured on a column basis, that it should be possible to reinitialize on a column basis to.
Will continue to figure this one out... (It seems the Virtex5 documentation on Partial Reconfiguration has some of the answers)