09-30-2011 04:12 AM - edited 09-30-2011 04:12 AM
i plan to use SERDES(LVDS) as backplane for my design. I have gone through the advnced IO section in the virtex5 user guide and have seen the ISERDES_NODELAY and OSERDES macros.
i have seen some nice application notes for implementing serdes in spartan fpgas but nothing for Virtex5?
Can anyone point me to some resources on properly implementing serdes(lvds) using V5 fpgas. I will be transmitting 100MBps data and clock from the master to 10 slaves(connected to backplane).What are the electrical considerations to be taken? Is a mictor connector with ribbon cables good for transmitting such signals or shall i use RF connectors with co-axial cables.
Kindly bear with my negligience as this is my first attempt at designing backplane.
thanks in advance
09-30-2011 05:36 AM
Have a look at Xapp855 16-Channel, DDR LVDS Interface with Per-Channel Alignment or Xapp860 16-Channel, DDR LVDS Interface with Real-Time Window Monitoring or Xapp856 SFI-4.1 16-Channel SDR Interface with Bus Alignment
10-02-2011 11:56 PM
thanks for the link.
The application note shows data rates of 600Mbps to 1400mbps. My requirement is to transmit data received from the USB interface(approx. 100Mbps). I had initially planned to use a 16bit parallel data bus to transmit the data to the 10 slaves connected on the backplane(i.e to use a parallel bus as backplane). In that case i will be transmitting using a clock of 6-7 MHz(16*6=96Mbps).My apprehensions are regarding running 16-20 lines for 1-2 feets that is why i am thinking of using serial link (16:1 SERDES) at 100Mbps.
Which method will be better for this requirement ?
10-14-2011 12:28 AM