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Explorer
Explorer
8,190 Views
Registered: ‎02-04-2011

SERDES for virtex5

Hi,

      i plan to use SERDES(LVDS) as backplane for my design. I have gone through the advnced IO section in the virtex5 user guide and have seen the ISERDES_NODELAY and OSERDES macros.

 

i have seen some nice application notes for implementing serdes in spartan fpgas but nothing for Virtex5?

Can anyone point me to some resources on properly implementing serdes(lvds) using V5 fpgas. I will be transmitting 100MBps data and clock from the master to 10 slaves(connected to backplane).What are the electrical considerations to be taken? Is a mictor connector with ribbon cables good for transmitting such signals or shall i use RF connectors with co-axial cables.

Kindly bear with my negligience as this is my first attempt at designing backplane.

 

thanks in advance

 

waris 

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6 Replies
Community Manager
Community Manager
8,183 Views
Registered: ‎08-08-2007

Re: SERDES for virtex5

From http://www.xilinx.com/support/documentation/virtex-5_application_notes.htm

Have a look at Xapp855 16-Channel, DDR LVDS Interface with Per-Channel Alignment  or Xapp860 16-Channel, DDR LVDS Interface with Real-Time Window Monitoring or  Xapp856 SFI-4.1 16-Channel SDR Interface with Bus Alignment

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Explorer
Explorer
8,169 Views
Registered: ‎02-04-2011

Re: SERDES for virtex5

thanks for the link.

The application note shows data rates of 600Mbps to 1400mbps. My requirement is to transmit data received from the USB interface(approx. 100Mbps). I had initially planned to use a 16bit parallel data bus to transmit the data to the 10 slaves connected on the backplane(i.e to use a parallel bus as backplane). In that case i will be transmitting using a clock of 6-7 MHz(16*6=96Mbps).My apprehensions are regarding running 16-20 lines for 1-2 feets that is why i am thinking of using serial link (16:1 SERDES) at 100Mbps.

 

Which method will be better for this requirement ?

 

 

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Explorer
Explorer
8,136 Views
Registered: ‎02-04-2011

Re: SERDES for virtex5

Help plz.

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Xilinx Employee
Xilinx Employee
8,133 Views
Registered: ‎04-15-2011

Re: SERDES for virtex5

In V5, the SERDES cannot support -16 data width in one link.
Because you data rate is not hign, I think you can write your Serdes module. The timing should be OK.
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Explorer
Explorer
8,096 Views
Registered: ‎02-04-2011

Re: SERDES for virtex5

What about the eletrical connections bet ween master and slaves(10)?

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Visitor sridhar_cool
Visitor
3,191 Views
Registered: ‎09-08-2016

Re: SERDES for virtex5

Can anyone explain me abouth the concept of deserializer and bit slip feature fo 7 series using mmcm

 

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