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Observer bjasionowski
Registered: ‎01-03-2013

Simulation and Implementation of System Monitor on Virtex 5

I am trying to simulate the system monitor for my Virtex 5 design so I can measure the temperature, Vccaux, and Vccint.


The HDL simulation appears to behave correctly, although I don't understand the values reported since the temperature, vccaux, and vccint all report the same value since do_out only changes once for all 3 values. This can't be correct, but I assume it had something to do with the simulation capability.


I am using the sequencer to step through those outputs and calibration, hence channels 8, 0, 1, and 2 are cycled.


I tried implementing my design and all the values appear to be wrong. The core voltage binary values are 0 and the temperature says something like 120 C after I run the binary word through the calculator. If I monitor the values through chipscope they seem more in line. I removed the heatsink to observe a spike in temperature. I saw the temp rise using chipscope, but the value being reported by the sysmon core was pretty much constant, so I think something isnt' right.


Any thoughts?

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