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Explorer
Explorer
9,581 Views
Registered: ‎04-08-2009

Strange JTAG Configuration behaviour ML605 Board

Hello i am using the ML605 Ev Board.

I also use the DDR3 memory and putted the phy_init_done signal on a led.

Every time i configure the board for the first time with impact over jtag the phy_init_done asserts and the deisgn works proper.

But if i reprogram it again the phy_init_done will not be asserted and if i press a reset via push button the design seems to hang up!?

Ethernet and the Design wont work anymore.

 

If i start the design via Flash memory on power up it also works fine.

 

It only happens when i reprogram it via JTAG for a second or more time...

If i power off the board and power it on again and use JTAG is can be successfully configured.

But then again a second program will fail with the described issues.

 

Does anyone know why this happens? Is there a Bug or issue?

 

The S2 Switch has the following configuration: Foto.JPG

 

Thanks for help.

0 Kudos
11 Replies
Highlighted
Xilinx Employee
Xilinx Employee
9,569 Views
Registered: ‎10-06-2011

Hi,

 

First, you'll want to make sure that you're using the latest version of iMPACT which is 14.2.

 

When programming, iMPACT will querry the bitstream. If the bitstream is determined to be a full configuration bitstream, JPROG will be issued and DONE will toggle. However, if the bitstream is something set to active reconfigure, iMPACT will not issue JPROG nor JSHUTDOWN. Your DONE will not toggle at that point.

 

So a few things to check, first, your bgn report to ensure the bitstream doesn't have active reconfig set. Second, you can always go into iMPACT's SVF mode and write out SVF for your programing operation. Look for JPRO command.


Regards,

Wei

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Highlighted
Explorer
Explorer
9,558 Views
Registered: ‎04-08-2009

OK, i added the bgn report. There are some warnings about the DDR3 memory, but i guess its only because i dont use all pins to it: 

Release 13.4 - Bitgen O.87xd (nt64)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
Loading device for application Rf_Device from file '6vlx240t.nph' in environment
C:\Xilinx\13.4\ISE_DS\ISE\.
   "EMAC_my_example_design" is an NCD, version 3.2, device xc6vlx240t, package
ff1156, speed -1
Opened constraints file EMAC_my_example_design.pcf.

Thu Sep 13 16:48:11 2012

C:\Xilinx\13.4\ISE_DS\ISE\bin\nt64\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g ConfigRate:2 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g InitPin:Pullup -g CsPin:Pullup -g DinPin:Pullup -g BusyPin:Pullup -g RdWrPin:Pullup -g HswapenPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g Disable_JTAG:No -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ConfigFallback:Enable -g BPI_page_size:1 -g OverTempPowerDown:Disable -g USR_ACCESS:None -g next_config_addr:None -g JTAG_SysMon:Enable -g DCIUpdateMode:Quiet -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g Match_cycle:Auto -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No EMAC_my_example_design.ncd 

INFO:Bitgen:40 - Replacing "Auto" with "2" for option "Match_cycle".  Most
   commonly, bitgen has determined and will use a specific value instead of the
   generic command-line value of "Auto".  Alternately, this message appears if
   the same option is specified multiple times on the command-line.  In this
   case, the option listed last will be used.
Summary of Bitgen Options:
+----------------------+----------------------+
| Option Name          | Current Setting      |
+----------------------+----------------------+
| Compress             | (Not Specified)*     |
+----------------------+----------------------+
| Readback             | (Not Specified)*     |
+----------------------+----------------------+
| CRC                  | Enable**             |
+----------------------+----------------------+
| DebugBitstream       | No**                 |
+----------------------+----------------------+
| ConfigRate           | 2**                  |
+----------------------+----------------------+
| StartupClk           | Cclk**               |
+----------------------+----------------------+
| CclkPin              | Pullup**             |
+----------------------+----------------------+
| DonePin              | Pullup*              |
+----------------------+----------------------+
| HswapenPin           | Pullup**             |
+----------------------+----------------------+
| M0Pin                | Pullup**             |
+----------------------+----------------------+
| M1Pin                | Pullup**             |
+----------------------+----------------------+
| M2Pin                | Pullup**             |
+----------------------+----------------------+
| ProgPin              | Pullup**             |
+----------------------+----------------------+
| InitPin              | Pullup**             |
+----------------------+----------------------+
| CsPin                | Pullup**             |
+----------------------+----------------------+
| DinPin               | Pullup**             |
+----------------------+----------------------+
| BusyPin              | Pullup**             |
+----------------------+----------------------+
| RdWrPin              | Pullup**             |
+----------------------+----------------------+
| TckPin               | Pullup**             |
+----------------------+----------------------+
| TdiPin               | Pullup**             |
+----------------------+----------------------+
| TdoPin               | Pullup**             |
+----------------------+----------------------+
| TmsPin               | Pullup**             |
+----------------------+----------------------+
| UnusedPin            | Pulldown**           |
+----------------------+----------------------+
| GWE_cycle            | 6**                  |
+----------------------+----------------------+
| GTS_cycle            | 5**                  |
+----------------------+----------------------+
| OverTempPowerDown    | Disable**            |
+----------------------+----------------------+
| LCK_cycle            | NoWait*              |
+----------------------+----------------------+
| Match_cycle          | 2                    |
+----------------------+----------------------+
| DONE_cycle           | 4**                  |
+----------------------+----------------------+
| Persist              | No*                  |
+----------------------+----------------------+
| DriveDone            | No**                 |
+----------------------+----------------------+
| DonePipe             | No**                 |
+----------------------+----------------------+
| Security             | None**               |
+----------------------+----------------------+
| UserID               | 0xFFFFFFFF**         |
+----------------------+----------------------+
| ActiveReconfig       | No*                  |
+----------------------+----------------------+
| Encrypt              | No**                 |
+----------------------+----------------------+
| EncryptKeySelect     | bbram*               |
+----------------------+----------------------+
| Key0                 | pick*                |
+----------------------+----------------------+
| StartCBC             | pick*                |
+----------------------+----------------------+
| HKey                 | pick*                |
+----------------------+----------------------+
| KeyFile              | (Not Specified)*     |
+----------------------+----------------------+
| DCIUpdateMode        | Quiet**              |
+----------------------+----------------------+
| ConfigFallback       | Enable**             |
+----------------------+----------------------+
| SelectMAPAbort       | Enable*              |
+----------------------+----------------------+
| BPI_page_size        | 1**                  |
+----------------------+----------------------+
| BPI_1st_read_cycle   | 1*                   |
+----------------------+----------------------+
| next_config_addr     | None**               |
+----------------------+----------------------+
| DoneSignalsPowerDown | Disable*             |
+----------------------+----------------------+
| InitSignalsError     | Enable*              |
+----------------------+----------------------+
| ICAP_Encryption      | Disable*             |
+----------------------+----------------------+
| SysmonPartialReconfig | Disable*             |
+----------------------+----------------------+
| SecAll               | No*                  |
+----------------------+----------------------+
| SecError             | No*                  |
+----------------------+----------------------+
| SecStatus            | No*                  |
+----------------------+----------------------+
| JTAG_SysMon          | Enable**             |
+----------------------+----------------------+
| Disable_JTAG         | No**                 |
+----------------------+----------------------+
| Partial              | (Not Specified)*     |
+----------------------+----------------------+
| TIMER_CFG            | None*                |
+----------------------+----------------------+
| TIMER_USR            | None*                |
+----------------------+----------------------+
| USR_ACCESS           | None**               |
+----------------------+----------------------+
| IEEE1532             | No*                  |
+----------------------+----------------------+
| Binary               | No**                 |
+----------------------+----------------------+
 *  Default setting.
 ** The specified setting matches the default setting.

There were 2 CONFIG constraint(s) processed from EMAC_my_example_design.pcf.

   CONFIG DCI_CASCADE = "26,25"
   CONFIG DCI_CASCADE = "36,35"

Running DRC.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0].u_
   phy_dqs_iob/u_iobuf_dqs/OB> is incomplete. The signal does not drive any load
   pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1].u_
   phy_dqs_iob/u_iobuf_dqs/OB> is incomplete. The signal does not drive any load
   pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_
   phy_dqs_iob/u_iobuf_dqs/OB> is incomplete. The signal does not drive any load
   pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3].u_
   phy_dqs_iob/u_iobuf_dqs/OB> is incomplete. The signal does not drive any load
   pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4].u_
   phy_dqs_iob/u_iobuf_dqs/OB> is incomplete. The signal does not drive any load
   pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5].u_
   phy_dqs_iob/u_iobuf_dqs/OB> is incomplete. The signal does not drive any load
   pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6].u_
   phy_dqs_iob/u_iobuf_dqs/OB> is incomplete. The signal does not drive any load
   pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_
   phy_dqs_iob/u_iobuf_dqs/OB> is incomplete. The signal does not drive any load
   pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[29].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[41].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[28].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[22].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[30].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[8].RAM32M0_RA
   MD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[40].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[7].RAM32M0_RA
   MD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[9].RAM32M0_RA
   MD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[11].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[39].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[17].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[26].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[6].RAM32M0_RA
   MD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[31].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[27].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[38].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[16].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[5].RAM32M0_RA
   MD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[12].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[18].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[19].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[4].RAM32M0_RA
   MD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[20].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[10].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[21].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[23].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[32].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[37].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[46].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[14].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[33].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[15].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[36].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/rams[0].RAM32M0_RAMA_D1_DPO
   > is incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/rams[0].RAM32M0_RAMD_D1_O>
   is incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/rams[1].RAM32M0_RAMA_D1_DPO
   > is incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/rams[1].RAM32M0_RAMD_D1_O>
   is incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[42].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[25].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[43].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[44].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[47].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[24].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[35].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[3].RAM32M0_RA
   MD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[13].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[0].RAM32M0_RA
   MD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[2].RAM32M0_RA
   MD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[34].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[45].RAM32M0_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[1].RAM32M0_RA
   MD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[18].RAM
   32M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[15].RAM
   32M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[1].RAM3
   2M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[9].RAM3
   2M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[5].RAM3
   2M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[7].RAM3
   2M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[10].RAM
   32M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[8].RAM3
   2M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/fifo_ram[0].RAM32M0_RA
   MD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.RAM32M0_RAMB_D1_DPO>
   is incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.RAM32M0_RAMD_D1_O> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/fifo_ram[1].RAM32M0_RA
   MA_D1_DPO> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/fifo_ram[1].RAM32M0_RA
   MB_D1_DPO> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/fifo_ram[1].RAM32M0_RA
   MD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[19].RAM
   32M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[17].RAM
   32M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[13].RAM
   32M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[16].RAM
   32M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[11].RAM
   32M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[0].RAM3
   2M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[42].RAM
   32M0_RAMA_D1_DPO> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[42].RAM
   32M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[4].RAM3
   2M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[3].RAM3
   2M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[35].RAM
   32M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[6].RAM3
   2M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[38].RAM
   32M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[37].RAM
   32M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[36].RAM
   32M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[20].RAM
   32M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[12].RAM
   32M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[40].RAM
   32M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[41].RAM
   32M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[32].RAM
   32M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[21].RAM
   32M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[2].RAM3
   2M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[34].RAM
   32M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[39].RAM
   32M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[26].RAM
   32M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[14].RAM
   32M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[28].RAM
   32M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[33].RAM
   32M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[27].RAM
   32M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[24].RAM
   32M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[25].RAM
   32M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[23].RAM
   32M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[22].RAM
   32M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[30].RAM
   32M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[29].RAM
   32M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <u_DDR_MIG_INF/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[31].RAM
   32M0_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:2045 - The MMCM_ADV block
   <u_DDR_MIG_INF/u_infrastructure/u_mmcm_adv> has CLKOUT pins that do not drive
   the same kind of BUFFER load. Routing from the different buffer types will
   not be phase aligned. 
DRC detected 0 errors and 111 warnings.  Please see the previously displayed
individual error or warning messages for more details.
Creating bit map...
Saving bit stream in "emac_my_example_design.bit".
Bitstream generation is complete.

 Finally, i wrote the program process to the svf file. I programmed it twice. I deleted most of the binary stuff:

 

// Created using Xilinx Cse Software [ISE - 13.4]
// Date: Tue Sep 18 09:33:23 2012

TRST OFF;
ENDIR IDLE;
ENDDR IDLE;
STATE RESET;
STATE IDLE;
FREQUENCY 1E6 HZ;
//Operation: Program -p 1 
TIR 0 ;
HIR 0 ;
TDR 0 ;
HDR 0 ;
TIR 8 TDI (ff) SMASK (ff) ;
HIR 0 ;
HDR 0 ;
TDR 1 TDI (00) SMASK (01) ;
//Loading device with 'idcode' instruction.
SIR 10 TDI (03c9) SMASK (03ff) ;
SDR 32 TDI (00000000) SMASK (ffffffff) TDO (f4250093) MASK (0fffffff) ;
//Boundary Scan Chain Contents
//Position 1: xccace
//Position 2: xc6vlx240t
TIR 0 ;
HIR 0 ;
TDR 0 ;
HDR 0 ;
TIR 0 ;
HIR 0 ;
TDR 0 ;
HDR 0 ;
TIR 8 TDI (ff) SMASK (ff) ;
HIR 0 ;
HDR 0 ;
TDR 1 TDI (00) SMASK (01) ;
//Loading device with 'idcode' instruction.
SIR 10 TDI (03c9) ;
SDR 32 TDI (00000000) TDO (f4250093) ;
//Loading device with 'bypass' instruction.
SIR 10 TDI (03ff) ;
// Loading device with a `jprogram` instruction. 
SIR 10 TDI (03cb) ;
// Loading device with a `isc_noop` instruction. 
SIR 10 TDI (03d4) ;
RUNTEST 100000 TCK;
// Check init_complete in ircapture.
//IR Capture using specified instruction.
SIR 10 TDI (03d4) TDO (0010) MASK (0010) ;
// Loading device with a `cfg_in` instruction. 
SIR 10 TDI (03c5) TDO (0000) MASK (0000) ;
SDR 73859647 TDI (000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000
000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200
000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002
000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000
020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000
000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200
000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002
000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000
020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000
000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200
000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002
000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000
020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000
00020000000200000002580000004000800600000002000000022706ea0ac0000006404000004002800640400000400180060000fb80400200060000000250000000400080060000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200
000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002
000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000
020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000260000000400080060000000228000000400080060000
0002000000026596960fc00000060000000000000000000000000000000000000000000000000000000000000000000000000000000000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ;
RUNTEST 10000E-6 SEC;
// reading the bootsts register contents.
// Loading device with a `cfg_in` instruction. 
// Loading device with a `cfg_in` instruction. 
SIR 10 TDI (03c5) ;
SDR 383 TDI (0000000200000002580000004000800600000002000000024001a00a0000000233554caa8000000000000000ffffffff) SMASK (7fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ;
// Loading device with a `cfg_out` instruction. 
SIR 10 TDI (03c4) ;
SDR 32 TDI (00000000) SMASK (ffffffff) TDO (00000000) MASK (1f000000) ;
STATE RESET;
// reading the status register contents.
// Loading device with a `cfg_in` instruction. 
// Loading device with a `cfg_in` instruction. 
SIR 10 TDI (03c5) ;
SDR 383 TDI (0000000200000002580000004000800600000002000000024003800a0000000233554caa8000000000000000ffffffff) SMASK (7fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ;
// Loading device with a `cfg_out` instruction. 
SIR 10 TDI (03c4) ;
SDR 32 TDI (00000000) SMASK (ffffffff) TDO (01180000) MASK (01180000) ;
// Loading device with a `jstart` instruction. 
SIR 10 TDI (03cc) ;
// INFO : The bitgen DCI match_cycle setting required that the RUNTEST wait time be
// INFO :  increased to ensure correct operation of generated System Ace files.
RUNTEST 10000 TCK;
//Loading device with 'Bypass' instruction.
SIR 10 TDI (03ff) TDO (0021) MASK (0020) ;
//Loading device with 'bypass' instruction.
SIR 10 TDI (03ff) ;
//Loading device with 'bypass' instruction.
SIR 10 TDI (03ff) ;
TIR 0 ;
HIR 10 TDI (03ff) SMASK (03ff) ;
HDR 1 TDI (00) SMASK (01) ;
TDR 0 ;
TIR 8 TDI (ff) SMASK (ff) ;
HIR 0 ;
HDR 0 ;
TDR 1 TDI (00) SMASK (01) ;
// Loading device with a `jstart` instruction. 
SIR 10 TDI (03cc) ;
// INFO : The bitgen DCI match_cycle setting required that the RUNTEST wait time be
// INFO :  increased to ensure correct operation of generated System Ace files.
RUNTEST 10000 TCK;
//Checking done pin status.
//Loading device with 'Bypass' instruction.
SIR 10 TDI (03ff) TDO (0021) MASK (0020) ;
TIR 0 ;
HIR 0 ;
TDR 0 ;
HDR 0 ;
SIR 18 TDI (03ffff) SMASK (03ffff) ;
SDR 2 TDI (00) SMASK (03) ;
//Operation: Program -p 1 
TIR 0 ;
HIR 0 ;
TDR 0 ;
HDR 0 ;
TIR 8 TDI (ff) SMASK (ff) ;
HIR 0 ;
HDR 0 ;
TDR 1 TDI (00) SMASK (01) ;
//Loading device with 'idcode' instruction.
SIR 10 TDI (03c9) SMASK (03ff) ;
SDR 32 TDI (00000000) SMASK (ffffffff) TDO (f4250093) MASK (0fffffff) ;
//Boundary Scan Chain Contents
//Position 1: xccace
//Position 2: xc6vlx240t
TIR 0 ;
HIR 0 ;
TDR 0 ;
HDR 0 ;
TIR 0 ;
HIR 0 ;
TDR 0 ;
HDR 0 ;
TIR 8 TDI (ff) SMASK (ff) ;
HIR 0 ;
HDR 0 ;
TDR 1 TDI (00) SMASK (01) ;
//Loading device with 'idcode' instruction.
SIR 10 TDI (03c9) ;
SDR 32 TDI (00000000) TDO (f4250093) ;
//Loading device with 'bypass' instruction.
SIR 10 TDI (03ff) ;
// Loading device with a `jprogram` instruction. 
SIR 10 TDI (03cb) ;
// Loading device with a `isc_noop` instruction. 
SIR 10 TDI (03d4) ;
RUNTEST 100000 TCK;
// Check init_complete in ircapture.
//IR Capture using specified instruction.
SIR 10 TDI (03d4) TDO (0010) MASK (0010) ;
// Loading device with a `cfg_in` instruction. 
SIR 10 TDI (03c5) TDO (0000) MASK (0000) ;
SDR 73859647 TDI (000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000
000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200
000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002
000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000
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000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ;
RUNTEST 10000E-6 SEC;
// reading the bootsts register contents.
// Loading device with a `cfg_in` instruction. 
// Loading device with a `cfg_in` instruction. 
SIR 10 TDI (03c5) ;
SDR 383 TDI (0000000200000002580000004000800600000002000000024001a00a0000000233554caa8000000000000000ffffffff) SMASK (7fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ;
// Loading device with a `cfg_out` instruction. 
SIR 10 TDI (03c4) ;
SDR 32 TDI (00000000) SMASK (ffffffff) TDO (00000000) MASK (1f000000) ;
STATE RESET;
// reading the status register contents.
// Loading device with a `cfg_in` instruction. 
// Loading device with a `cfg_in` instruction. 
SIR 10 TDI (03c5) ;
SDR 383 TDI (0000000200000002580000004000800600000002000000024003800a0000000233554caa8000000000000000ffffffff) SMASK (7fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ;
// Loading device with a `cfg_out` instruction. 
SIR 10 TDI (03c4) ;
SDR 32 TDI (00000000) SMASK (ffffffff) TDO (01180000) MASK (01180000) ;
// Loading device with a `jstart` instruction. 
SIR 10 TDI (03cc) ;
// INFO : The bitgen DCI match_cycle setting required that the RUNTEST wait time be
// INFO :  increased to ensure correct operation of generated System Ace files.
RUNTEST 10000 TCK;
//Loading device with 'Bypass' instruction.
SIR 10 TDI (03ff) TDO (0021) MASK (0020) ;
//Loading device with 'bypass' instruction.
SIR 10 TDI (03ff) ;
//Loading device with 'bypass' instruction.
SIR 10 TDI (03ff) ;
TIR 0 ;
HIR 10 TDI (03ff) SMASK (03ff) ;
HDR 1 TDI (00) SMASK (01) ;
TDR 0 ;
TIR 8 TDI (ff) SMASK (ff) ;
HIR 0 ;
HDR 0 ;
TDR 1 TDI (00) SMASK (01) ;
// Loading device with a `jstart` instruction. 
SIR 10 TDI (03cc) ;
// INFO : The bitgen DCI match_cycle setting required that the RUNTEST wait time be
// INFO :  increased to ensure correct operation of generated System Ace files.
RUNTEST 10000 TCK;
//Checking d

 The active reprogram is set to off. Thats right or?

 

I work for a big project and we will use 13.4 for all. So thats why i really dont want to change to 14.2 at the moment.

Thanks for help.

 

 

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Xilinx Employee
Xilinx Employee
9,548 Views
Registered: ‎10-06-2011

Hi,

 

Your bgn report looks fine. And iMPACT SVF shows that you should have JPROG issued as well. So, if this is a big project, I'll strongly recommend that you get your local sales or FAE in to take a look and if possible, grab another ML605 board.

 

I tried with your dip switch setting on my board and I get Done to toggle fine with my bitstream. With your SVF, you can try this. Remove everything after this.

// Loading device with a `jprogram` instruction. 
SIR 10 TDI (03cb) ;
// Loading device with a `isc_noop` instruction. 
SIR 10 TDI (03d4) ;
RUNTEST 100000 TCK;

 

Then do this from ISE command line. 

 

impact -batch

>setmode -bs

>setcable -port auto

>adddevice -p 1 -file <svf_file>

>play

 

After you enter play, DONE will go low, if not, there is something else going on. I'll suspect it's more of a board or device issue, so a FAE coming in with another ML605 board should help. If that works, but doing PROG via IMPACT doesn't work, it's likely a SW issue.

 

In any case, this may worth opening a Xilinx case through support to investigate more.

 

Regards,

Wei

 

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Explorer
Explorer
9,537 Views
Registered: ‎04-08-2009

I also think this is an issue with the ML605 board.

I have 3 of them here and its the same behavior with the others.

 

I remember that i had an old design where i also putted the phy_init_done to a LED and it always worked.

After every reprogram.

I tested this design again and i also produced this error there.

 

Maybe it something wrong with the board or even impact and the usb connection.

 

Its just strange that i works very stable but only if it programmed with jtag after power on once or loading from the flash memory.

 

In practic there will be an owned designed board. And ususally the design will load from the flash. So i see no problem till now.

 

But i wanted to clear up why this happens. Because i dont think that i will solve this problem with Chipscope or SW.

And also in the simulation theres no problem.

 

Could it be an timing problem? 

 

I have a MMCM at the input which generates all clock needed by the design.

I constrained all clock outputs in the ucf. All frequencies are reached in the place and route report.

I will try the mentioned impact commands with the svf file.

 

So this error is kind of confusing.

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Xilinx Employee
Xilinx Employee
9,526 Views
Registered: ‎10-06-2011

Hi,

 

If JPROG doesn't cause your DONE to toggle (which should also completely wipe your design clean), what you're doing is active partial reconfiguration. With design containing SRL16/LUTRAM/BRAM, all these content can be corrupted. With primitives like GT and MMCM(PLL/DCM), you can potentially have them interrupted and placed in a bad state since you may be glitching their inputs unintentionally.

 

Regards,
Wei

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Explorer
Explorer
9,520 Views
Registered: ‎04-08-2009

My design contains much BRAMS, Ethernet MAC, DDR3 Mig and so on.

So i can potentially avoid this by just power the board on again and then use the jtag again to configure??

 

This would be logic, till now the board always configure well after power on and load from bitfile or once by jtag.

 

 

 

 

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Xilinx Employee
Xilinx Employee
9,516 Views
Registered: ‎10-06-2011

Hi,

 

You should be able to push the PROG button on the board and that should work as well. (As soon as you push the button, DONE should go low and you should see INIT drop low as long as you're holding the PROG button) JPROG is effectively trying to achieve the same as PROG assuming the problem is simply limited to somehow the SW isn't getting JPROG to the part.

 

Regards,

Wei

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Explorer
Explorer
9,507 Views
Registered: ‎04-08-2009

Sorry i tested it, its the same issue.

Maybe something is wrong with mig. 

 

I will generate an extra reset psh button for the MIG.

 

Maybe it helps.

 

The INIT led is on after pushing the button, but again the phy_init_does not go on. And if i press my reset the design seems to hang up like the lcd doesnt work and my heartbeat signals stops.

 

Also there could be an error in the ucf file. I will add this:

# The xc6vlx240tff1156-1 part is chosen for this example design.
# This value should be modified to match your device.
CONFIG PART = xc6vlx240tff1156-1;

# Locate the Tri-Mode Ethernet MAC instance
INST "*v6_emac" LOC = "TEMAC_X0Y0";

NET  "RESET"           LOC = G26;  # Centre push-button 

INST SYSCLK_N LOC = H9 ;
INST SYSCLK_P LOC = J9 ;
#NET SYSCLK_P TNM_NET = sysclk;
#TIMESPEC TS_sysclk = PERIOD sysclk_grp 5 ns HIGH 50 %;

# Ethernet GTX_CLK high quality 125 MHz reference clock
NET "SYSCLK_P" TNM_NET = "SYSCLK_P_clk";
TIMEGRP "SYSCLK_P_clk_ref_gtx" = "SYSCLK_P_clk";
TIMESPEC "TS_SYSCLK_P_clk_ref_gtx" = PERIOD "SYSCLK_P_clk_ref_gtx" 8 ns HIGH 50 %;

# Ethernet GTX_CLK high quality 125 MHz reference clock
NET "GTX_CLK" TNM_NET = "ref_gtx_clk";
TIMEGRP "emac_refresh_clk_ref_gtx" = "ref_gtx_clk";
TIMESPEC "TS_emac_refresh_clk_ref_gtx" = PERIOD "emac_refresh_clk_ref_gtx" 8 ns HIGH 50 %;

# Ethernet GMII PHY-side receive clock
NET "GMII_RX_CLK" TNM_NET = "phy_clk_rx";
TIMEGRP "emac_refresh_clk_phy_rx" = "phy_clk_rx";
TIMESPEC "TS_emac_refresh_clk_phy_rx" = PERIOD "emac_refresh_clk_phy_rx" 7.5 ns HIGH 50 %;

# IDELAYCTRL 200 MHz reference clock
NET "REFCLK" TNM_NET  = "clk_ref_clk";
TIMEGRP "ref_clk" = "clk_ref_clk";
TIMESPEC "TS_ref_clk" = PERIOD "ref_clk" 5 ns HIGH 50 %;


NET "REFCLK_TTE" TNM_NET  = "clk_reftte_clk";
TIMEGRP "reftte_clk" = "clk_reftte_clk";
TIMESPEC "TS_reftte_clk" = PERIOD "reftte_clk" 10 ns HIGH 50 %;

###############################################################################
# PHYSICAL INTERFACE CONSTRAINTS
# The following constraints are necessary for proper operation, and are tuned
# for this example design. They should be modified to suit your design.
###############################################################################

# GMII physical interface constraints
# -----------------------------------------------------------------------------

# Set the IDELAY values on the PHY inputs, tuned for this example design.
# These values should be modified to suit your design.
INST "*gmii?ideldv"    IDELAY_VALUE = 26;
INST "*gmii?ideld0"    IDELAY_VALUE = 26;
INST "*gmii?ideld1"    IDELAY_VALUE = 26;
INST "*gmii?ideld2"    IDELAY_VALUE = 26;
INST "*gmii?ideld3"    IDELAY_VALUE = 26;
INST "*gmii?ideld4"    IDELAY_VALUE = 26;
INST "*gmii?ideld5"    IDELAY_VALUE = 26;
INST "*gmii?ideld6"    IDELAY_VALUE = 26;
INST "*gmii?ideld7"    IDELAY_VALUE = 26;
INST "*gmii?ideler"    IDELAY_VALUE = 26;
INST "*gmii_rxc_delay" IDELAY_VALUE = 0;
INST "*gmii_rxc_delay" SIGNAL_PATTERN = CLOCK;

#ADDITIONAL Start

# Group all IDELAY-related blocks to use a single IDELAYCTRL
INST "*dlyctrl" IODELAY_GROUP = gmii_idelay;
INST "*ideld?"  IODELAY_GROUP = gmii_idelay;
INST "*ideldv"  IODELAY_GROUP = gmii_idelay;
INST "*ideler"  IODELAY_GROUP = gmii_idelay;
INST "*gmii_rxc_delay" IODELAY_GROUP = gmii_idelay;

# The following constraints work in conjunction with IDELAY_VALUE settings to
# check that the GMII receive bus remains in alignment with the rising edge of
# GMII_RX_CLK, to within 2ns setup time and 0 hold time.
INST "GMII_RXD<?>" TNM = "gmii_rx";
INST "GMII_RX_DV"  TNM = "gmii_rx";
INST "GMII_RX_ER"  TNM = "gmii_rx";
TIMEGRP "gmii_rx" OFFSET = IN 2 ns VALID 2 ns BEFORE "GMII_RX_CLK" RISING;


# Constrain the GMII physical interface flip-flops to IOBs
INST "*gmii?RXD_TO_MAC*"  IOB = true;
INST "*gmii?RX_DV_TO_MAC" IOB = true;
INST "*gmii?RX_ER_TO_MAC" IOB = true;
INST "*gmii?GMII_TXD_?"   IOB = true;
INST "*gmii?GMII_TX_EN"   IOB = true;
INST "*gmii?GMII_TX_ER"   IOB = true;
#ADDITIONAL END


NET "PHY_RESET" LOC = "AH13";
INST "GMII_TXD<0>" LOC = "AM11";
INST "GMII_TXD<1>" LOC = "AL11";
INST "GMII_TXD<2>" LOC = "AG10";
INST "GMII_TXD<3>" LOC = "AG11";
INST "GMII_TXD<4>" LOC = "AL10";
INST "GMII_TXD<5>" LOC = "AM10";
INST "GMII_TXD<6>" LOC = "AE11";
INST "GMII_TXD<7>" LOC = "AF11";
INST "GMII_TX_EN"  LOC = "AJ10";
INST "GMII_TX_ER"  LOC = "AH10";
INST "GMII_TX_CLK" LOC = "AH12";
INST "GMII_RXD<0>" LOC = "AN13";
INST "GMII_RXD<1>" LOC = "AF14";
INST "GMII_RXD<2>" LOC = "AE14";
INST "GMII_RXD<3>" LOC = "AN12";
INST "GMII_RXD<4>" LOC = "AM12";
INST "GMII_RXD<5>" LOC = "AD11";
INST "GMII_RXD<6>" LOC = "AC12";
INST "GMII_RXD<7>" LOC = "AC13";
INST "GMII_RX_DV"  LOC = "AM13";
INST "GMII_RX_ER"  LOC = "AG12";
INST "GMII_RX_CLK" LOC = "AP11";

#NET "SM_FAN_PWM" LOC = "L10"; ## 1 on Q24
INST "MIG_RESET"	LOC = "K21";
#look other pins
INST "IOPad<0>"                      LOC = "AL8";    ## 29 on U4, A1 on U27
INST "IOPad<1>"                      LOC = "AK8";    ## 25 on U4, B1 on U27
#INST "IOPad<1>"                      LOC = "AH27";    ## 25 on U4, B1 on U27
INST "IOPad<2>"                     LOC = "AC9";    ## 24 on U4, C1 on U27
INST "IOPad<3>"                     LOC = "AD10";   ## 23 on U4, D1 on U27
INST "IOPad<4>"                     LOC = "C8";     ## 22 on U4, D2 on U27
INST "IOPad<5>"                     LOC = "B8";     ## 21 on U4, A2 on U27
INST "IOPad<6>"                     LOC = "E9";     ## 20 on U4, C2 on U27
INST "IOPad<7>"                      LOC = "E8";     ## 19 on U4, A3 on U27
INST "IOPad<8>"                     LOC = "A8";     ## 8  on U4, B3 on U27
INST "IOPad<9>"                     LOC = "A9";     ## 7  on U4, C3 on U27
INST "IOPad<10>"                     LOC = "D9";     ## 6  on U4, D3 on U27
INST "IOPad<11>"                     LOC = "C9";     ## 5  on U4, C4 on U27
INST "IOPad<12>"                     LOC = "D10";    ## 4  on U4, A5 on U27
INST "IOPad<13>"                     LOC = "C10";    ## 3  on U4, B5 on U27
INST "IOPad<14>"                     LOC = "F10";    ## 2  on U4, C5 on U27
INST "IOPad<15>"                     LOC = "F9";     ## 1  on U4, D7 on U27
INST "IODir<0>"                     LOC = "AH8";    ## 55 on U4, D8 on U27
INST "IODir<1>"                     LOC = "AG8";    ## 18 on U4, A7 on U27
INST "IODir<2>"                     LOC = "AP9";    ## 17 on U4, B7 on U27
INST "IODir<3>"                     LOC = "AN9";    ## 16 on U4, C7 on U27
INST "IODir<4>"                     LOC = "AF10";   ## 11 on U4, C8 on U27
INST "IODir<5>"                     LOC = "AF9";    ## 10 on U4, A8 on U27
INST "IODir<6>"                     LOC = "AL9";    ## 9  on U4, G1 on U27
INST "IODir<7>"                     LOC = "AA23";   ## 26 on U4
INST "IODir<8>"                     LOC = "AF24";   ## 34 on U4, F2 on U27
INST "IODir<9>"                     LOC = "AF25";   ## 36 on U4, E2 on U27
INST "IODir<10>"                     LOC = "W24";    ## 39 on U4, G3 on U27
INST "IODir<11>"                     LOC = "V24";    ## 41 on U4, E4 on U27
INST "IODir<12>"                     LOC = "H24";    ## 47 on U4, E5 on U27
INST "IODir<13>"                     LOC = "H25";    ## 49 on U4, G5 on U27
INST "IODir<14>"                      LOC = "P24";    ## 51 on U4, G6 on U27
INST "IODir<15>"                      LOC = "R24";    ## 53 on U4, H7 on U27
INST "PLLLocked"                LOC = "AB33";   ## E16 on J64
INST "FBOin"                LOC = "AA34";   ## E15 on J64 #further locked
INST "VCXO_Ctr"             LOC = "W30";    ## K17 on J64
#INST "TPRDY"            	LOC = "V30";    ## K16 on J64
INST "Toggle"					LOC = "AP24";   ## 2   on LED DS16
INST "TimeMarkIndicator" 	LOC = "AE21";   ## 2   on LED DS19
NET "EMACCLIENTRXDVLD" LOC = "A10"; #further locked
NET "FBO_out"			LOC = "AD21"; #LED on DS17 (West)
NET "PSGOUTDEBUG"					LOC = "AH27"; #DS 20

#connect to LCD##################################################
NET "lcd_data<0>"                    LOC = "AD14";   ## 4   on J41
NET "lcd_data<1>"                    LOC = "AK11";   ## 3   on J41
NET "lcd_data<2>"                    LOC = "AJ11";   ## 2   on J41
NET "lcd_data<3>"                    LOC = "AE12";   ## 1   on J41
NET "lcd_en"                      LOC = "AK12";   ## 9   on J41
NET "lcd_rs"                     LOC = "T28";    ## 11  on J41
NET "lcd_rw"                     LOC = "AC14";   ## 10  on J41
#################################################################

################################################################################
# I/O STANDARDS
################################################################################

NET  "ddr3_dq[*]"                               IOSTANDARD = SSTL15_T_DCI;
NET  "ddr3_addr[*]"                             IOSTANDARD = SSTL15;
NET  "ddr3_ba[*]"                               IOSTANDARD = SSTL15;
NET  "ddr3_ras_n"                               IOSTANDARD = SSTL15;
NET  "ddr3_cas_n"                               IOSTANDARD = SSTL15;
NET  "ddr3_we_n"                                IOSTANDARD = SSTL15;
NET  "ddr3_reset_n"                             IOSTANDARD = SSTL15;
NET  "ddr3_cke[*]"                              IOSTANDARD = SSTL15;
NET  "ddr3_odt[*]"                              IOSTANDARD = SSTL15;
NET  "ddr3_cs_n[*]"                             IOSTANDARD = SSTL15;
NET  "ddr3_dm[*]"                               IOSTANDARD = SSTL15;
NET  "RESET"                               		IOSTANDARD = SSTL15;
## NET  "sys_clk_p"                                IOSTANDARD = LVDS_25;
## NET  "sys_clk_n"                                IOSTANDARD = LVDS_25;
#NET  "clk_ref_p"                                IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
#NET  "clk_ref_n"                                IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
## NET  "sda"                                      IOSTANDARD = LVCMOS25;
## NET  "scl"                                      IOSTANDARD = LVCMOS25;
#NET  "sys_rst"                                  IOSTANDARD = SSTL15;      ## ML605 
NET  "phy_init_done"                            IOSTANDARD = LVCMOS25;
#NET  "error"                                    IOSTANDARD = LVCMOS25;
NET  "ddr3_dqs_p[*]"                            IOSTANDARD = DIFF_SSTL15_T_DCI;
NET  "ddr3_dqs_n[*]"                            IOSTANDARD = DIFF_SSTL15_T_DCI;
NET  "ddr3_ck_p[*]"                             IOSTANDARD = DIFF_SSTL15;
NET  "ddr3_ck_n[*]"                             IOSTANDARD = DIFF_SSTL15;


CONFIG PROHIBIT = H22;  
CONFIG PROHIBIT = F21;  
CONFIG PROHIBIT = B20;  
CONFIG PROHIBIT = F19;  
CONFIG PROHIBIT = C13;  
CONFIG PROHIBIT = M12;  
CONFIG PROHIBIT = L13; 
CONFIG PROHIBIT = K14;  
CONFIG PROHIBIT = F25;  
CONFIG PROHIBIT = C29;  
CONFIG PROHIBIT = C28;  
CONFIG PROHIBIT = D24; 

###############################################################################
#DCI_CASCADING
#Syntax : CONFIG DCI_CASCADE = "<master> <slave1> <slave2> ..";
###############################################################################
CONFIG DCI_CASCADE = "26 25";
CONFIG DCI_CASCADE = "36 35";

NET  "RESET"           LOC = G26;  # Centre push-button 
##################################################################################
# Location Constraints
##################################################################################
NET  "ddr3_dq[0]"                                LOC = "J11" ;          #Bank 35
NET  "ddr3_dq[1]"                                LOC = "E13" ;          #Bank 35
NET  "ddr3_dq[2]"                                LOC = "F13" ;          #Bank 35
NET  "ddr3_dq[3]"                                LOC = "K11" ;          #Bank 35
NET  "ddr3_dq[4]"                                LOC = "L11" ;          #Bank 35
NET  "ddr3_dq[5]"                                LOC = "K13" ;          #Bank 35
NET  "ddr3_dq[6]"                                LOC = "K12" ;          #Bank 35
NET  "ddr3_dq[7]"                                LOC = "D11" ;          #Bank 35
NET  "ddr3_dq[8]"                                LOC = "M13" ;          #Bank 35
NET  "ddr3_dq[9]"                                LOC = "J14" ;          #Bank 35
NET  "ddr3_dq[10]"                               LOC = "B13" ;          #Bank 35
NET  "ddr3_dq[11]"                               LOC = "B12" ;          #Bank 35
NET  "ddr3_dq[12]"                               LOC = "G10" ;          #Bank 35
NET  "ddr3_dq[13]"                               LOC = "M11" ;          #Bank 35
NET  "ddr3_dq[14]"                               LOC = "C12" ;          #Bank 35
NET  "ddr3_dq[15]"                               LOC = "A11" ;          #Bank 35
NET  "ddr3_dq[16]"                               LOC = "G11" ;          #Bank 35
NET  "ddr3_dq[17]"                               LOC = "F11" ;          #Bank 35
NET  "ddr3_dq[18]"                               LOC = "D14" ;          #Bank 35
NET  "ddr3_dq[19]"                               LOC = "C14" ;          #Bank 35
NET  "ddr3_dq[20]"                               LOC = "G12" ;          #Bank 35
NET  "ddr3_dq[21]"                               LOC = "G13" ;          #Bank 35
NET  "ddr3_dq[22]"                               LOC = "F14" ;          #Bank 35
NET  "ddr3_dq[23]"                               LOC = "H14" ;          #Bank 35
NET  "ddr3_dq[24]"                               LOC = "C19" ;          #Bank 26
NET  "ddr3_dq[25]"                               LOC = "G20" ;          #Bank 26
NET  "ddr3_dq[26]"                               LOC = "E19" ;          #Bank 26
NET  "ddr3_dq[27]"                               LOC = "F20" ;          #Bank 26
NET  "ddr3_dq[28]"                               LOC = "A20" ;          #Bank 26
NET  "ddr3_dq[29]"                               LOC = "A21" ;          #Bank 26
NET  "ddr3_dq[30]"                               LOC = "E22" ;          #Bank 26
NET  "ddr3_dq[31]"                               LOC = "E23" ;          #Bank 26
NET  "ddr3_dq[32]"                               LOC = "G21" ;          #Bank 26
NET  "ddr3_dq[33]"                               LOC = "B21" ;          #Bank 26
NET  "ddr3_dq[34]"                               LOC = "A23" ;          #Bank 26
NET  "ddr3_dq[35]"                               LOC = "A24" ;          #Bank 26
NET  "ddr3_dq[36]"                               LOC = "C20" ;          #Bank 26
NET  "ddr3_dq[37]"                               LOC = "D20" ;          #Bank 26
NET  "ddr3_dq[38]"                               LOC = "J20" ;          #Bank 26
NET  "ddr3_dq[39]"                               LOC = "G22" ;          #Bank 26
NET  "ddr3_dq[40]"                               LOC = "D26" ;          #Bank 25
NET  "ddr3_dq[41]"                               LOC = "F26" ;          #Bank 25
NET  "ddr3_dq[42]"                               LOC = "B26" ;          #Bank 25
NET  "ddr3_dq[43]"                               LOC = "E26" ;          #Bank 25
NET  "ddr3_dq[44]"                               LOC = "C24" ;          #Bank 25
NET  "ddr3_dq[45]"                               LOC = "D25" ;          #Bank 25
NET  "ddr3_dq[46]"                               LOC = "D27" ;          #Bank 25
NET  "ddr3_dq[47]"                               LOC = "C25" ;          #Bank 25
NET  "ddr3_dq[48]"                               LOC = "C27" ;          #Bank 25
NET  "ddr3_dq[49]"                               LOC = "B28" ;          #Bank 25
NET  "ddr3_dq[50]"                               LOC = "D29" ;          #Bank 25
NET  "ddr3_dq[51]"                               LOC = "B27" ;          #Bank 25
NET  "ddr3_dq[52]"                               LOC = "G27" ;          #Bank 25
NET  "ddr3_dq[53]"                               LOC = "A28" ;          #Bank 25
NET  "ddr3_dq[54]"                               LOC = "E24" ;          #Bank 25
NET  "ddr3_dq[55]"                               LOC = "G25" ;          #Bank 25
NET  "ddr3_dq[56]"                               LOC = "F28" ;          #Bank 25
NET  "ddr3_dq[57]"                               LOC = "B31" ;          #Bank 25
NET  "ddr3_dq[58]"                               LOC = "H29" ;          #Bank 25
NET  "ddr3_dq[59]"                               LOC = "H28" ;          #Bank 25
NET  "ddr3_dq[60]"                               LOC = "B30" ;          #Bank 25
NET  "ddr3_dq[61]"                               LOC = "A30" ;          #Bank 25
NET  "ddr3_dq[62]"                               LOC = "E29" ;          #Bank 25
NET  "ddr3_dq[63]"                               LOC = "F29" ;          #Bank 25
#NET  "ddr3_addr[15]"                             LOC = "C15" ;          #Bank 36
NET  "ddr3_addr[14]"                             LOC = "D15" ;          #Bank 36
NET  "ddr3_addr[13]"                             LOC = "J15" ;          #Bank 36
NET  "ddr3_addr[12]"                             LOC = "H15" ;          #Bank 36
NET  "ddr3_addr[11]"                             LOC = "M15" ;          #Bank 36
NET  "ddr3_addr[10]"                             LOC = "M16" ;          #Bank 36
NET  "ddr3_addr[9]"                              LOC = "F15" ;          #Bank 36
NET  "ddr3_addr[8]"                              LOC = "G15" ;          #Bank 36
NET  "ddr3_addr[7]"                              LOC = "B15" ;          #Bank 36
NET  "ddr3_addr[6]"                              LOC = "A15" ;          #Bank 36
NET  "ddr3_addr[5]"                              LOC = "J17" ;          #Bank 36
NET  "ddr3_addr[4]"                              LOC = "D16" ;          #Bank 36
NET  "ddr3_addr[3]"                              LOC = "E16" ;          #Bank 36
NET  "ddr3_addr[2]"                              LOC = "B16" ;          #Bank 36
NET  "ddr3_addr[1]"                              LOC = "A16" ;          #Bank 36
NET  "ddr3_addr[0]"                              LOC = "L14" ;          #Bank 36
NET  "ddr3_ba[2]"                                LOC = "L15" ;          #Bank 36
NET  "ddr3_ba[1]"                                LOC = "J19" ;          #Bank 36
NET  "ddr3_ba[0]"                                LOC = "K19" ;          #Bank 36
NET  "ddr3_ras_n"                                LOC = "L19" ;          #Bank 36
NET  "ddr3_cas_n"                                LOC = "C17" ;          #Bank 36
NET  "ddr3_we_n"                                 LOC = "B17" ;          #Bank 36
NET  "ddr3_reset_n"                              LOC = "E18" ;          #Bank 36
NET  "ddr3_cke[0]"                               LOC = "M18" ;          #Bank 36
NET  "ddr3_odt[0]"                               LOC = "F18" ;          #Bank 36
NET  "ddr3_cs_n[0]"                              LOC = "K18" ;          #Bank 36
NET  "ddr3_dm[0]"                                LOC = "E11" ;          #Bank 35
NET  "ddr3_dm[1]"                                LOC = "B11" ;          #Bank 35
NET  "ddr3_dm[2]"                                LOC = "E14" ;          #Bank 35
NET  "ddr3_dm[3]"                                LOC = "D19" ;          #Bank 26
NET  "ddr3_dm[4]"                                LOC = "B22" ;          #Bank 26
NET  "ddr3_dm[5]"                                LOC = "A26" ;          #Bank 25
NET  "ddr3_dm[6]"                                LOC = "A29" ;          #Bank 25
NET  "ddr3_dm[7]"                                LOC = "A31" ;          #Bank 25
## NET  "sys_clk_p"                                 LOC = "J9" ;          #Bank 34
## NET  "sys_clk_n"                                 LOC = "H9" ;          #Bank 34
#NET  "clk_ref_p"                                 LOC = "J9" ;          #Bank 34
#NET  "clk_ref_n"                                 LOC = "H9" ;          #Bank 34
## NET  "sda"                                       LOC = "F9" ;          #Bank 34
## NET  "scl"                                       LOC = "F10" ;          #Bank 34
#NET  "sys_rst"                                   LOC = "H10" ;          #ML605 CPU_RESET switch
NET  "phy_init_done"                             LOC = "AH28" ;         #ML605 GPIO LED 3
#NET  "error"                                     LOC = "AE22" ;         #ML605 GPIO LED 2
NET  "ddr3_dqs_p[0]"                             LOC = "D12" ;          #Bank 35
NET  "ddr3_dqs_n[0]"                             LOC = "E12" ;          #Bank 35
NET  "ddr3_dqs_p[1]"                             LOC = "H12" ;          #Bank 35
NET  "ddr3_dqs_n[1]"                             LOC = "J12" ;          #Bank 35
NET  "ddr3_dqs_p[2]"                             LOC = "A13" ;          #Bank 35
NET  "ddr3_dqs_n[2]"                             LOC = "A14" ;          #Bank 35
NET  "ddr3_dqs_p[3]"                             LOC = "H19" ;          #Bank 26
NET  "ddr3_dqs_n[3]"                             LOC = "H20" ;          #Bank 26
NET  "ddr3_dqs_p[4]"                             LOC = "B23" ;          #Bank 26
NET  "ddr3_dqs_n[4]"                             LOC = "C23" ;          #Bank 26
NET  "ddr3_dqs_p[5]"                             LOC = "B25" ;          #Bank 25
NET  "ddr3_dqs_n[5]"                             LOC = "A25" ;          #Bank 25
NET  "ddr3_dqs_p[6]"                             LOC = "H27" ;          #Bank 25
NET  "ddr3_dqs_n[6]"                             LOC = "G28" ;          #Bank 25
NET  "ddr3_dqs_p[7]"                             LOC = "C30" ;          #Bank 25
NET  "ddr3_dqs_n[7]"                             LOC = "D30" ;          #Bank 25
NET  "ddr3_ck_p[0]"                              LOC = "G18" ;          #Bank 36
NET  "ddr3_ck_n[0]"                              LOC = "H18" ;          #Bank 36
NET  "ddr3_ck_p[1]"                              LOC = "K16" ;          #Bank 36  #further locked
NET  "ddr3_ck_n[1]"                              LOC = "L16" ;          #Bank 36  #further locked
NET "REFCLK_10M"											LOC = "AA33";

######################################################################################
##Place RSYNC OSERDES and IODELAY:                                                  ##
######################################################################################

##Site: C29 -- Bank 25
INST "u_DDR_MIG_INF/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_oserdes_rsync"
  LOC = "OLOGIC_X1Y139";
INST "u_DDR_MIG_INF/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_odelay_rsync"
  LOC = "IODELAY_X1Y139";

INST "u_DDR_MIG_INF/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_bufr_rsync"
  LOC = "BUFR_X1Y6";

##Site: M12 -- Bank 35
INST "u_DDR_MIG_INF/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_oserdes_rsync"
  LOC = "OLOGIC_X2Y139";
INST "u_DDR_MIG_INF/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_odelay_rsync"
  LOC = "IODELAY_X2Y139";

INST "u_DDR_MIG_INF/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_bufr_rsync"
  LOC = "BUFR_X2Y6";

######################################################################################
##Place CPT OSERDES and IODELAY:                                                    ##
######################################################################################

##Site: C13 -- Bank 35
INST "u_DDR_MIG_INF/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[0].u_oserdes_cpt"
  LOC = "OLOGIC_X2Y137";
INST "u_DDR_MIG_INF/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[0].u_odelay_cpt"
  LOC = "IODELAY_X2Y137";

##Site: L13 -- Bank 35
INST "u_DDR_MIG_INF/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[1].u_oserdes_cpt"
  LOC = "OLOGIC_X2Y141";
INST "u_DDR_MIG_INF/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[1].u_odelay_cpt"
  LOC = "IODELAY_X2Y141";

##Site: K14 -- Bank 35
INST "u_DDR_MIG_INF/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[2].u_oserdes_cpt"
  LOC = "OLOGIC_X2Y143";
INST "u_DDR_MIG_INF/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[2].u_odelay_cpt"
  LOC = "IODELAY_X2Y143";

##Site: F21 -- Bank 26
INST "u_DDR_MIG_INF/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[3].u_oserdes_cpt"
  LOC = "OLOGIC_X1Y179";
INST "u_DDR_MIG_INF/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[3].u_odelay_cpt"
  LOC = "IODELAY_X1Y179";

##Site: B20 -- Bank 26
INST "u_DDR_MIG_INF/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[4].u_oserdes_cpt"
  LOC = "OLOGIC_X1Y181";
INST "u_DDR_MIG_INF/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[4].u_odelay_cpt"
  LOC = "IODELAY_X1Y181";

##Site: F25 -- Bank 25
INST "u_DDR_MIG_INF/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[5].u_oserdes_cpt"
  LOC = "OLOGIC_X1Y137";
INST "u_DDR_MIG_INF/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[5].u_odelay_cpt"
  LOC = "IODELAY_X1Y137";

##Site: C28 -- Bank 25
INST "u_DDR_MIG_INF/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[6].u_oserdes_cpt"
  LOC = "OLOGIC_X1Y141";
INST "u_DDR_MIG_INF/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[6].u_odelay_cpt"
  LOC = "IODELAY_X1Y141";

##Site: D24 -- Bank 25
INST "u_DDR_MIG_INF/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[7].u_oserdes_cpt"
  LOC = "OLOGIC_X1Y143";
INST "u_DDR_MIG_INF/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[7].u_odelay_cpt"
  LOC = "IODELAY_X1Y143";


######################################################################################
## MMCM_ADV CONSTRAINTS                                                             ##
######################################################################################

INST "u_DDR_MIG_INF/u_infrastructure/u_mmcm_adv"      LOC = "MMCM_ADV_X0Y8"; #Banks 16, 26, 36

 

I finally removed all pins (IOdir and iopads), which are not really on the ML605 board.

But even if i reset the MIG with an own pushbutton the behjavior of hanging up by reset is visible.

But i found something very interesting and you maybe can help to clear up.

 

When the board is powered on the DS29 LED for DDR3_PWR_GD is on.

When i do a first programming is stays on and the phy_init_done will assert properly.

 

But if i reprogram it by jtag or the PROG Switch button the DS29 LED is not asserted for the time of reprogramming.

Then a failure programming with the mentioned issues happens.

Then randomly if the DS29 stays on and after i press the PROG Switch the design will be programmed successful!

 

So could this be a power issue or something like this? Maybe its the same issue described in : http://www.xilinx.com/support/answers/39767.htm ?

 

 

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Explorer
Explorer
9,474 Views
Registered: ‎04-08-2009

An addition:

 

i i removed the DDR3 memory. The DS29 LED will never goes off and stays on. So it only happens if the module is inserted.

Also if the DS29 turns off during programming the design fails.

Now i press my reset button (see ucf) and the design will hang up.

When it hangs up the DS29 LED also turns off.

If i now programm it after hang up after own reset by push button it will always successfully programmed.

 

Also if i always hold the reset button before pressing the PROG button the design will always programmed successful.

I release the reset button after a second and the phy_init_done and so on works. 

The DS29 Led also never turns off in this case.

 

Hope someone can clear this strange behavior.

 

Seems to be something with the hardware i guess

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Adventurer
Adventurer
3,479 Views
Registered: ‎10-13-2011

Did you resolve your issue? Was it similar to the solution you posted in: http://www.xilinx.com/support/answers/39767.htm ?

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Explorer
Explorer
2,892 Views
Registered: ‎04-08-2009

Yes thats the Problem.

There is another issue.

If you have the board connected the plug socket and change the DDR Memory, i cant get the phy_init_done getting asserted.

The solution is to remove the power plug and connect it to another plug socket.

There seem to be some rest voltages etc.

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