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Observer aliasnikhil
Observer
9,143 Views
Registered: ‎06-06-2012

Trouble integrating 200MHz differential clock with sysgen module ML605 board

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Hi,

 

I created my design using the System Generator. I want to use the differential clock on the ML605 board.

 

I read some posts on this forum which advise on how to instantiate an IBUFGDS primitive (in a wrapper .v file) and give the output of the primitive to the sysgen module (instantiated under the same wrapper). I opened the sysgen .v files but I am confused as to which is the real clock and which should be connected to my IBUFGDS clock output. It has a lot of modules and I do not understand reason for their presence. Please help me understand them.

 

Note: My sysgen project name is 'XXX'

 

module xlclockdriver (sysclk, sysclr, sysce, clk, clr, ce, ce_logic);

....

endmodule

 

module default_clock_driver_XXX (ce_1, clk_1, sysclk, sysce, sysce_clr);

...

* xlclockdriver instantiated inside this module

endmodule

 

module XXX_cw(clk...)

...

endmodule

 

 

Looking from the code, I see that 'sysclk' in first module is input and 'clk' is output and it contains a statement:

assign clk = sysclk;

Does this mean that I assgin the clock output of my IBUFGDS to 'sysclk'?

 

Please help.

 

Thanks!

-Nik

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1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
14,186 Views
Registered: ‎11-28-2007

Re: Trouble integrating 200MHz differential clock with sysgen module ML605 board

Jump to solution

Here is what I recommend:

 

Create a separate wrapper file say top.v

In top.v, instantiate IBUFGDS, BUFG, etc and xxx_cw block

Connect BUFG output to clk input of xxx_cw

 


@aliasnikhil wrote:

Hi,

 

I created my design using the System Generator. I want to use the differential clock on the ML605 board.

 

I read some posts on this forum which advise on how to instantiate an IBUFGDS primitive (in a wrapper .v file) and give the output of the primitive to the sysgen module (instantiated under the same wrapper). I opened the sysgen .v files but I am confused as to which is the real clock and which should be connected to my IBUFGDS clock output. It has a lot of modules and I do not understand reason for their presence. Please help me understand them.

 

Note: My sysgen project name is 'XXX'

 

module xlclockdriver (sysclk, sysclr, sysce, clk, clr, ce, ce_logic);

....

endmodule

 

module default_clock_driver_XXX (ce_1, clk_1, sysclk, sysce, sysce_clr);

...

* xlclockdriver instantiated inside this module

endmodule

 

module XXX_cw(clk...)

...

endmodule

 

 

Looking from the code, I see that 'sysclk' in first module is input and 'clk' is output and it contains a statement:

assign clk = sysclk;

Does this mean that I assgin the clock output of my IBUFGDS to 'sysclk'?

 

Please help.

 

Thanks!

-Nik




Cheers,
Jim

View solution in original post

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3 Replies
Xilinx Employee
Xilinx Employee
14,187 Views
Registered: ‎11-28-2007

Re: Trouble integrating 200MHz differential clock with sysgen module ML605 board

Jump to solution

Here is what I recommend:

 

Create a separate wrapper file say top.v

In top.v, instantiate IBUFGDS, BUFG, etc and xxx_cw block

Connect BUFG output to clk input of xxx_cw

 


@aliasnikhil wrote:

Hi,

 

I created my design using the System Generator. I want to use the differential clock on the ML605 board.

 

I read some posts on this forum which advise on how to instantiate an IBUFGDS primitive (in a wrapper .v file) and give the output of the primitive to the sysgen module (instantiated under the same wrapper). I opened the sysgen .v files but I am confused as to which is the real clock and which should be connected to my IBUFGDS clock output. It has a lot of modules and I do not understand reason for their presence. Please help me understand them.

 

Note: My sysgen project name is 'XXX'

 

module xlclockdriver (sysclk, sysclr, sysce, clk, clr, ce, ce_logic);

....

endmodule

 

module default_clock_driver_XXX (ce_1, clk_1, sysclk, sysce, sysce_clr);

...

* xlclockdriver instantiated inside this module

endmodule

 

module XXX_cw(clk...)

...

endmodule

 

 

Looking from the code, I see that 'sysclk' in first module is input and 'clk' is output and it contains a statement:

assign clk = sysclk;

Does this mean that I assgin the clock output of my IBUFGDS to 'sysclk'?

 

Please help.

 

Thanks!

-Nik




Cheers,
Jim

View solution in original post

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Observer aliasnikhil
Observer
9,121 Views
Registered: ‎06-06-2012

Re: Trouble integrating 200MHz differential clock with sysgen module ML605 board

Jump to solution

Hi Jim,

 

Thanks for the reply.

 

Just to confirm, you say that I should remove the  instantiations of the "xlclockdriver" and "default_clock_driver_XXX" modules. Just instantiate the XXX_cw module and the IBUFGDS modules and connect the output clock to 'clk' input of XXX_cw module?

 

Also, why would I need a BUFG if I am already using an IBUFGDS? Should I use a BUFG in between the IBUFGDS and my module?

 

I have attached the final HDL file (which I think is the complete wrapper file generated by sysgen). Please take a look and let me know. The 2 clock_driver modules above, generated by sysgen, also pass signals like sysclr etc which I am not sure will disrupt my XXX module if those modules are removed.

 

 

Thanks!

-Nik

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Xilinx Employee
Xilinx Employee
9,105 Views
Registered: ‎11-28-2007

Re: Trouble integrating 200MHz differential clock with sysgen module ML605 board

Jump to solution

Yes, just instantiate XXX_cw in your top level verilog module. IBUFGDS is just a speical input buffer. It doesn't include a BUFG in it. You will need to add it yourself.

 


@aliasnikhil wrote:

Hi Jim,

 

Thanks for the reply.

 

Just to confirm, you say that I should remove the  instantiations of the "xlclockdriver" and "default_clock_driver_XXX" modules. Just instantiate the XXX_cw module and the IBUFGDS modules and connect the output clock to 'clk' input of XXX_cw module?

 

Also, why would I need a BUFG if I am already using an IBUFGDS? Should I use a BUFG in between the IBUFGDS and my module?

 

I have attached the final HDL file (which I think is the complete wrapper file generated by sysgen). Please take a look and let me know. The 2 clock_driver modules above, generated by sysgen, also pass signals like sysclr etc which I am not sure will disrupt my XXX module if those modules are removed.

 

 

Thanks!

-Nik




Cheers,
Jim
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