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Visitor
Visitor
9,812 Views
Registered: ‎06-04-2014

UCF file modification of ML605 Ethernet MAC tri-mode core

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Hello:

My FPGA board is virtex-6 ML605, and I use ISE 14.5 to generate the embedded MAC wrapper.

And I chose SGMII tranceiver.

The original .ucf file of the physical interface constain was modified as:

---------------------------------------------------------------------------------------------------------------

NET "MGTCLK_N" LOC = "H5"; #
NET "MGTCLK_P" LOC = "H6"; #
NET "TXP" LOC = "A3";
NET "TXN" LOC = "A4";
NET "RXP" LOC = "B5";
NET "RXN" LOC = "B6";
INST "*gtx0_v6_gtxwizard_i?gtxe1_i" LOC = "GTXE1_X0Y19"; #TNM = "fifo_read"; #"GTXE1_X0Y8";

------------------------------------------------------------------------------------------------------------

to fit the SGMII interface.

 

But, I have a question.

The top module of the example design named as "v6_emac_v1_6_example_design"  has more input/output port than that described in the .ucf file.

For example, the "RESET" port in the top module is not assgined to any location in the .ucf file. 

There are a lot of ports that seem to be unconnected.

Should I mannully add additional pin locations in the .ucf file?

 

Thank you,

Chen-Yang Lin 

 

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Xilinx Employee
Xilinx Employee
17,119 Views
Registered: ‎08-01-2008
you can manually modify the ucf file by referring master ucf of ML605 board.
Thanks and Regards
Balkrishan
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Xilinx Employee
Xilinx Employee
17,120 Views
Registered: ‎08-01-2008
you can manually modify the ucf file by referring master ucf of ML605 board.
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
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Xilinx Employee
Xilinx Employee
9,793 Views
Registered: ‎02-06-2013

Hi

 

The latest version of the core will give you the full UCF.

 

Attached the UCF from the latest core which you can use.

Regards,

Satish

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Visitor
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Registered: ‎06-04-2014

hello,

Thank you for your advice.

In my situation, the top file (.vhd) has much more I/O port than the default .ucf.

The default ucf only defines ports such as,

----------------the UCF--------------------------

CONFIG PART = xc6vlx240tff1156-1;

 

Net mgtclk_n LOC = H5;
Net mgtclk_p LOC = H6;

Net txp LOC = A3;
Net txn LOC = A4;
Net rxp LOC = B5;
Net rxn LOC = B6;

INST "*gtx0_v6_gtxwizard_i?gtxe1_i" LOC = "GTXE1_X0Y19"; #TNM = "fifo_read"; #"GTXE1_X0Y8";

-----------------------------------------

 

---------the entity of top module------------------------

entity v6_emac_v2_6_example_design is
port(

-- Client receiver interface
EMACCLIENTRXDVLD : out std_logic;
EMACCLIENTRXFRAMEDROP : out std_logic;
EMACCLIENTRXSTATS : out std_logic_vector(6 downto 0);
EMACCLIENTRXSTATSVLD : out std_logic;
EMACCLIENTRXSTATSBYTEVLD : out std_logic;

-- Client transmitter interface
CLIENTEMACTXIFGDELAY : in std_logic_vector(7 downto 0);
EMACCLIENTTXSTATS : out std_logic;
EMACCLIENTTXSTATSVLD : out std_logic;
EMACCLIENTTXSTATSBYTEVLD : out std_logic;

-- MAC control interface
CLIENTEMACPAUSEREQ : in std_logic;
CLIENTEMACPAUSEVAL : in std_logic_vector(15 downto 0);

--EMAC-transceiver link status
EMACCLIENTSYNCACQSTATUS : out std_logic;
EMACANINTERRUPT : out std_logic;

-- SGMII interface
TXP : out std_logic;
TXN : out std_logic;
RXP : in std_logic;
RXN : in std_logic;
PHYAD : in std_logic_vector(4 downto 0);

-- SGMII-transceiver reference clock buffer input
MGTCLK_P : in std_logic;
MGTCLK_N : in std_logic;

-- Asynchronous reset
RESET : in std_logic

);

------------------------------------------------------

But other I/O ports in the top file seems to be missing in the ucf file.

Do I need to add all I/O to the .ucf mannually ?   

 

Thank you

 

Chen-Yang Lin

 

 

 

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