Unable to modify SIM_TX_ELEC_IDLE_LEVELvalue to z

[vlsi_sata]

Hi,

I am using Virtex 6 GTX for SATA FPGA simulations.

During simulations in OOB phase, when TXELECIDLE is 1, Line has to be 'z' inbetween bursts.

But I see an 'X' instead. Which is wrong.

When I tried to modify this using SIM_TX_ELEC_IDLE_LEVEL parameter of GTXE1, I am getting error from that:

ERROR: Invalid SIM_TX_ELEC_IDLE_LEVEL value z

(Tried with caps Z too.. same issue)

Could you pls help me out of this 'x' and make line z.

Many Thanks

[pratham · Accepted solution]

@vlsi_sata It should work, What tool version are you using and which simulator? Is this error seen on ISIM?

[vlsi_sata]

Hi Pratham,

Ya, It worked. Actually small z is not working. Only Caps Z is working.

I realized it today.

Thanks for your prompt reply.

[pratham]

@vlsi_sata Great! please close this thread.