06-07-2011 02:30 AM
I have a Microblaze Design with some user logic running on a Virtex 5 LX30T-FF665. The clock is located at LOC= AC18.
During MAP I receive the error:
ERROR:Place:1014 - Unroutable Placement! A clock IOB / PLL clock component pair have been found that are not placed at a
routable clock IOB / PLL site pair. The CLKIO component <fpga_0_clk_1_sys_clk_pin> is placed at site <IOB_X1Y27>. The
corresponding PLL component <clock_generator_0/clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst> is placed at
site <PLL_ADV_X0Y1>. The clock IO site can use the fast path between the IOB and the PLL if both the IOB & PLL are
placed in the same half of the device (TOP or BOTTOM). This placement is UNROUTABLE in PAR and therefore, this error
condition should be fixed in your design. You may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote
this message to a WARNING in order to generate an NCD file. This NCD file can then be used in FPGA Editor to debug
the problem. A list of all the COMP.PINS used in this clock placement rule is listed below. These examples can be
used directly in the .ucf file to demote this ERROR to a WARNING.
< NET "fpga_0_clk_1_sys_clk_pin" CLOCK_DEDICATED_ROUTE = FALSE; >
< PIN "clock_generator_0/clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst.CLKIN1" CLOCK_DEDICATED_ROUTE =
If I do this than PAR can not route this signal
WARNING:Route:436 - The router has detected an unroutable situation for one or more connections. The router will finish
the rest of the design and leave them as unrouted. The cause of this behavior is either an issue with the placement
or unroutable placement constraints. To allow you to use FPGA editor to isolate the problems, the following is a list
of (up to 10) such unroutable connections:
Unroutable signal: fpga_0_clk_1_sys_clk_pin_IBUF pin:
Why can a global clock signal not routed to a PLL?. How may I overcome this error.
06-07-2011 04:16 AM
In Virtex-5, PLLs in the top half of the device are driven by the global clock pins in bank3 and PLLs in the bottom half of the device are driven by the global clock pins in bank4.
In your design, you are using a PLL (PLL_ADV_X0Y1) in top half and its CLKIN is connected to GCLK (IOB_X1Y27) from bank 4. It is violation and MAP is unable to mapping it so giving an error.
If you are using PLL_ADV_X0Y1, CLKIN1 of the PLL should be connected to any of the following pins of bank 3.
Hope this helps and removes your error.
You can have documentaion about this in Virtex-5 user guide (please use below link)
Refer to page no:100
06-07-2011 04:18 AM
Clocks are special nets, requiring special care.
Special drivers are used to drive these (in most cases) large nets.
Therefore only a limited number of pins are qualified to serve as clock inputs.
You find these in the datasheet and the pin names in the pinout drawings and some tools like PlanAhead give you a hint too.
All other I/Os are unlikely to be routed to clock driving ressources like PLLs or GBUFs, or cause other problems when used.
Additionally, larger FPGAs are divided into special clock regions, and that's why even not every valid clock input can be routed to any PLL. It's just a limitation of the hardware. FPGAs are not based on magic, but physics.
Have a nice synthesis
06-07-2011 04:38 AM
I tried IO_l06P_GC_3 (F12) to and had the same trouble. Why does MAP place the PLL into the top half if the clock is connected to the bottom half? How can I place the PLL manually?
I need an example.
06-08-2011 12:49 AM
since PLLs are rare elements inside an FPGA they need to be instantiated one way or another.
When you have an instance of some element/primitive, you can apply an atttribute with a location constraint in your HDL, or add some location constraint in your UCF file.
Tools like PlanAhead or Floorplanner can assist you in this task.
Have a nice synthesis
06-08-2011 03:08 AM
For example if you want to use PLL_ADV_X0Y1 use LOC constraint as below
INST “instance_name “ LOC=PLL_ADV_X0Y1;