01-03-2008 05:42 AM - edited 01-03-2008 05:43 AM
01-03-2008 06:25 AM
01-03-2008 01:24 PM
04-14-2008 06:16 AM
09-11-2008 11:09 AM
So how to connect the MGTREFCLKP/MGTREFCLKN in the unused GTP_DUAL tiles
in the Partially Unused GTP_DUAL Column not used for clock forwarding?
As in Table 10-6 = Floating, No Connection OR
as on page 212 they can be connected to GND
09-11-2008 02:04 PM
05-05-2009 09:08 AM
Extending this question to LXT/FXT cross-family compatibility:
Suppose I wanted to maintain pin compatibility betweeen an LXT part and an FXT part, where the FXT part has extra MGT tiles that the LXT part lacks.
Should I treat these phantom tiles in the LXT as if they were present? (as in: supply filtered power, ground the RX inputs, etc)
Specifically -- the FXT parts in an FGG1136 package include GTX tiles 124 and 126 -- these are listed as NOPAD/UNCONNECTED in the LXT.
The ML555 schematic shows these unused GTP sections with MGTAVCC tied to 1.2V (exceeds the ABS MAX specs), and
MGTAVCCPLL connected to 1.0V (too low for GTP used in the LXT parts, but correct for GTX used in FXT parts)
(page 27 of ML555R1_Schematics.pdf).
Is this an error?
05-06-2009 07:56 AM
This is a mistake in the ML555 schematic, actually there are two mistakes here.
1) A resistor divider should not have been used to generate the tie-off voltages. These should have either been left unconnected o tied to the 1.0V and 1.2V planes
2) The resistor values for R370 and R372 should be swapped to generate 1.0V for the MGTAVCC and 1.2V for the MGTAVCCPLL for Virtex-5 LX50T.
R370 = 1.18K ohm, R372 = 845 ohm
The GTP Banks 124 and 126 are unbonded in the LX50T-FF1156 so there is nothing in the device that will be damaged.