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jshand
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Registered: ‎01-02-2008

Unused RocketIO Virtex 5 pins

Do the unused RocketIO pins (AVCC, TXP, RXP, AVTTTX, REFCLKP) need to be tied up or down on the Virtex 5?
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barriet
Xilinx Employee
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Registered: ‎08-13-2007

Jeff,
 
From the user guide, http://www.xilinx.com/support/documentation/user_guides/ug196.pdf (Virtex-5 RocketIO GTP Transceiver User Guide)
 
==
It is recommended to connect the unused differential input pin clock pair to ground or
leave it floating (both MGTREFCLKP and MGTREFCLKN).
...
 
Completely unused GTP_DUAL column
There are rare cases when all GTP_DUAL tiles in an LXT or SXT device will never be
used, meaning the entire GTP_DUAL column is unused. In this case, connect the
following pins or pin pairs of all GTP_DUAL tiles of the device to ground:
♦ MGTRXP/MGTRXN
♦ MGTTXP/MGTTXN
♦ MGTREFCLKP/MGTREFCLKN
♦ MGTAVCC (see Note)
♦ MGTAVCCPLL (see Note)
♦ MGTAVTTRX (see Note)
♦ MGTAVTTTX (see Note)
♦ MGTAVTTRXC (see Note)
♦ MGTRREF
Note: If Boundary-Scan is part of the product verification, make sure that these analog supply
voltage pins of all GTP_DUAL tiles are powered: MGTAVCC, MGTAVCCPLL, MGTAVTTRX,
MGTATTTX, and MGTAVTTRXC.

• Partially used GTP_DUAL column
When unused GTP_DUAL tiles of a column are used to forward a clock, the
MGTAVCC and MGTAVCCPLL pins need to be powered using the required filter
circuit as outlined in Figure 10-4, page 206. The MGTAVTTRX and MGTAVTTTX pins
need to be powered but filtering is not required. In this case, the differential pin pairs
MGTRXN/MGTRXP and MGTTXN/MGTTXP can be left floating. If the unused
GTP_DUAL tiles are not used for clock forwarding,
 
==
 
Keep in mind that the same package can have a different number of transceivers, depending on the device size. If you want to plan for device migration and possible future usage, it can be good to look at these details prior to board design.
ADEPT can be useful resource here:
Please be advised that ADEPT is not currently officially released Xilinx software and is not directly supported by Xilinx Technical Support. But many users, as well as many of us within Xilinx, find it to be very useful.
 
Cheers,
bt


Message Edited by timpe on 01-03-2008 08:43 AM
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jshand
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Registered: ‎01-02-2008

bt,
 
Thanks for your reply.  
 
Specifically, I'm using a VLX220T. 
 
All of the GTP_DUAL tiles are unused except for 114.  My understanding is that every pin within the unused GTP_DUAL tiles 112, 116, etc should all be tied to ground including the RX outputs.  Is that accurate?
 
For Bank 114, I'm using AVTTTX, RXP0,RXN0,REFCLKP,REFCLKP, and AVCCPLL.
 
My confusion lies in the last line from the users guide (page 218) stating "If the unused GTP_DUAL tiles are not used for clock forwarding, all analog supply pins must be powered but do not require filtering."  From the first paragraph of the users guide, I thought unused GTP_DUAL tiles should all be grounded.  Can you clarify?
 
Jeff
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mcgett
Xilinx Employee
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Registered: ‎01-03-2008

You misread the documentation, the phrase is "when unused GTP_DUAL tiles of colum are used to forward a clock".

Each GTP_DUAL has buffers to transmit the reference clock to the tile above or below it and these are powered off of the GTP analog supplies.  If you want to do this, or to use JTAG boundary scan,  then you need to provide the correct voltage levels to these supplies.  However, since you won't be operating the transceiver the quality of the supply doesn't matter and you do not need to filter the supply and can tie it directly to the source.

On the TXP/TXN outputs being tied to ground you can do this without any issues as the drivers will not be on, but I don't know of any particular reason why this would be needed.
------Have you tried typing your question into Google? If not you should before posting.
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a.pozzebon
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Registered: ‎04-14-2008

I read the UG196 (v1.6) pag 218 Table 10-5.
What are MGTTTX and MGTTRX signals?
You say me: "connect the following pins or pin pairs of all GTP_DUAL tiles of the device to ground:
♦ MGTRXP/MGTRXN
♦ MGTTXP/MGTTXN
♦ MGTREFCLKP/MGTREFCLKN
♦ MGTAVCC (see Note)
♦ MGTAVCCPLL (see Note)
♦ MGTAVTTRX (see Note)
♦ MGTAVTTTX (see Note)
♦ MGTAVTTRXC (see Note)
♦ MGTRREF
 
but in the UG196 there is a different indication:
 
♦ MGTTXP/MGTTXN
♦ MGTREFCLKP/MGTREFCLKN
♦ MGTAVTTRXC (see Note)
 
 this signals have to be left floating (unconnected).
 
Other differences: if i want to use boundary scan, which are the pins that i've to connect to power? (the UG196 say me only the MGTAVCC pin, you say me somthing different)
At this moment i don't know if i will use boundary scan... can i power this pins and then not to use boundary scan?
Thank you 
 
 
 
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mbalfour
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Registered: ‎09-11-2008

So how to connect the MGTREFCLKP/MGTREFCLKN in the unused GTP_DUAL tiles
in the Partially Unused GTP_DUAL Column not used for clock forwarding?

As in Table 10-6 = Floating, No Connection                    OR

as on page 212 they can be connected to GND

 

MB

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mcgett
Xilinx Employee
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Registered: ‎01-03-2008

Any of the above, it doesn't have any effect on the device operation. 
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ncputhuff
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Registered: ‎05-05-2009

Extending this question to LXT/FXT cross-family compatibility:

 

Suppose I wanted to maintain pin compatibility betweeen an LXT part and an FXT part, where the FXT part has extra MGT tiles that the LXT part lacks.

Should I treat these phantom tiles in the LXT as if they were present?  (as in: supply filtered power, ground the RX inputs, etc)

 

Specifically -- the FXT parts in an FGG1136 package include GTX tiles 124 and 126 -- these are listed as NOPAD/UNCONNECTED in the LXT.

 

The ML555 schematic shows these unused GTP sections with MGTAVCC tied to 1.2V (exceeds the ABS MAX specs), and

MGTAVCCPLL connected to 1.0V (too low for GTP used in the LXT parts, but correct for GTX used in FXT parts)

(page 27 of ML555R1_Schematics.pdf).

Is this an error?

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mcgett
Xilinx Employee
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Registered: ‎01-03-2008

This is a mistake in the ML555 schematic, actually there are two mistakes here.

 

1) A resistor divider should not have been used to generate the tie-off voltages. These should have either been left unconnected o tied to the 1.0V and 1.2V planes

2) The resistor values for R370 and R372 should be swapped to generate 1.0V for the MGTAVCC and 1.2V for the MGTAVCCPLL for Virtex-5 LX50T.

      R370 = 1.18K ohm, R372 = 845 ohm

 

The GTP Banks 124 and 126 are unbonded in the LX50T-FF1156 so there is nothing in the device that will be damaged.

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