Using BRAM instead of SRAM in Virtex-5 FPGA

[syedhuqa]

Hi,

I am working on a project where we are capturing signals from an ADC using a Virtex-5 FPGA and the samples are being stored on a 128K x 256 SRAM from where the data samples are acquired by a PC. I believe the Virtex-5 provides an option for a BRAM and while I understand that the depth is nowhere close to what the SRAM provides, I'd like to make use of the BRAM option in the Virtex-5 as a buffer to hold the samples temporarily until they are acquired by the PC. How difficult would this be to implement ?

[vsrunga]

Hi,

I do not think any difficulty in imlementing it you can use BRAM core to store ADC samples.

Please visit below web page and go trough the documentation for writing and reading details.

http://www.xilinx.com/products/intellectual-property/Block_Memory_Generator.htm

Regards,

Vanitha

[bassman59]

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@syedhuqa wrote:

Hi,

I am working on a project where we are capturing signals from an ADC using a Virtex-5 FPGA and the samples are being stored on a 128K x 256 SRAM from where the data samples are acquired by a PC. I believe the Virtex-5 provides an option for a BRAM and while I understand that the depth is nowhere close to what the SRAM provides, I'd like to make use of the BRAM option in the Virtex-5 as a buffer to hold the samples temporarily until they are acquired by the PC. How difficult would this be to implement ?

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it's actually a lot easier to store your samples in the FPGA's BRAM instead of in external SRAM. 

All you need to do is to infer the amount of memory you need. Make it dual-port so the read side can be comlpetely decoupled from the write side.