05-04-2011 02:15 PM
05-04-2011 02:54 PM
If a master bank has no DCI in it, but subsequent IO in other backs require it (DCI control), then that master bank must use the VRP, VRN pins to the appropriate resistors.
I doubt seriosly that nayone would do this, as it is better to use the first bank where DCI is used, as the master. In fact, I doubt the first case (above) is supported (as it doesn't make any sense).
As for not trusting the tools to do what is required, I can't help you there. In FPGA_Editor, it will be clear that the attributes are set properly (DCI, or not). And, if there are no errors in bitgen (a bitstream results), you are done.
If I didn't trust the tools to do their job I would never complete a single project. It is more than enough to deal with the occasional bug than to deal with every feature, to prove everything is perfect. If you have the time to do that, wow!
If you need the IO pins in the subsequent backs (can not afford to use them as VRN, VRP), then use them. Now that they are used as IO, if the cascade isn't properly implemented, an error will result (as those banks requiring DCI will either have to be slaves to the master bank, or those pins will be usurped for the resistors).
05-04-2011 04:06 PM
Thanks Austin for the quick reply.
In my design, the DDR3 interfaces were completely generated by the Xilinx Core Gen (MIG). In response to your comment : "I doubt seriosly that anyone would do this, as it is better to use the first bank where DCI is used, as the master. In fact, I doubt the first case (above) is supported (as it doesn't make any sense)." For DDR3 Interface 1, the Xilinx MIG used bank 23 as the DCI Master bank eventhough this bank is not used at all by the DDR3 interface.
Thanks once again for your help,
05-05-2011 03:39 PM
1- Is there a way to see if the VRP / VRN pins are actually used for DCI cascading?
If I recall correctly, one of the implementation tools will print out some information on the DCI cascade to let you know that is being used. However, I'm unable to recall which one at the moment.
2- Can the VRP / VRN pins of a Master Bank that does not use DCI (itself) can be used as regular IOs?
No. You need the reference resistors. Note that at one time an input pin using DCI was required to enable the master so you'll see some old MIG designs with a dummy input pin. Since then that restriction was removed and the dummy pin was removed.
Also note that this is a valid use case. There are some scenarios in DDR3 in V6 that require every pin in the bank (either internally or externally) including the VRN/VRP to fit 3 bytes in one bank. Utlizing the neighboring bank for the DCI master helps considerably with byte packing at the expense of requiring Vcco of that bank to be 1.5V.
05-05-2011 06:01 PM
Thanks for your reply.
As you mentioned for the DDR3 byte packing, this is my situation and I really do not want to try to move DDR3 critical signals out of the bank if I do not have too. There are a lot of pin allocation rules for the DDR3 mem controllers and I am trying to avoid modifying the pinout provided by the Xilinx MIG SW. Freeing up the VRP/VRN pins in the "slave" DDR3 banks may require moving out 10+ signals in each bank (8 data + related DQS + prohibited signal used for internal use).
I really need to find a way to validate that the DCI cascading is setup properly. The ISE SW seems to be "happy" with the DCI cascading that I have setup (using non-DCI Banks as the Master Bank). However, the ISE SW also does not pop-up an error or warning if I do use the VRP / VRN pins of the non-DCI Master Bank as regular IOs (and this is very strange).
Once again, thanks for your help.
05-18-2011 11:48 AM
just for your information, I just received a response from the Xilinx support team that this is a DRC bug and a Pinout Report bug.
05-18-2011 12:09 PM
Marquis, is this a show-stopper bug, or is there a workaround?
Thanks for pursuing this to its logical conclusion.
-- Bob Elkind