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Explorer
Explorer
9,005 Views
Registered: ‎11-28-2011

V5 DCM Phase Adjust in Simulation

Have an implementation of dynamic phase shift of the V5 DCM using VARIABLE CENTER mode. The input clock is 32MHz. For some odd reason, though the phase shifts are commanded and are acknowledged (PS_DONE) by the DCM, the actual phases are not changing (i.e. through measuring the clkin and clkout phases) in simulation.

 

This is a functional simulation using VCS Version I-2014.03-1_Full64.  Is there a particular issue with the simulatin model of the DCM, or is it possible I'm doing something wrong?

 

I've attached some waveforms for reference:

DCM_initial indicates the initial state. Can cleary see all waveforms are aligned

dcm_pscmd_128: Can see a phase shift of 3417ps (clk_in1 to rx_clk32_out)

dcm_pscmd_255:  Can see that this yields the same phase delta as above. Hence not affect.

 

I've stepped through all of the phase shift commands and it yields the same phase difference. 

 

This implement works in hardware, so it's odd that we can't simulate the behavior

 

 

 DCM_ADV
 #(
    .CLK_FEEDBACK          ("1X"                )
  , .CLKDV_DIVIDE          (2.0                 )  
  , .CLKFX_DIVIDE          (1                   )
  , .CLKFX_MULTIPLY        (7                   )
  , .CLKIN_DIVIDE_BY_2     ("FALSE"             )
  , .CLKIN_PERIOD          (31.250              )
  , .CLKOUT_PHASE_SHIFT    ("VARIABLE_CENTER"   )
  , .DCM_AUTOCALIBRATION   ("TRUE"              )
  , .DCM_PERFORMANCE_MODE  ("MAX_SPEED"         )
  , .DESKEW_ADJUST         ("SYSTEM_SYNCHRONOUS")
  , .DFS_FREQUENCY_MODE    ("HIGH"              )
  , .DLL_FREQUENCY_MODE    ("LOW"               )
  , .DUTY_CYCLE_CORRECTION ("TRUE"              )
  , .FACTORY_JF            (16'hF0F0            )
  , .PHASE_SHIFT           (0                   )
  , .STARTUP_WAIT          ("FALSE"             )
  , .SIM_DEVICE            ("VIRTEX5"           ) 
  ) 
  DCM_ADV_INST
  (
    .CLKFB    (CLKFB_IN        )
  , .CLKIN    (CLKOUTDCM0_CLKIN)
  , .DADDR    (GND_BUS_7[6:0]  )
  , .DCLK     (GND_BIT         )
  , .DEN      (GND_BIT         )
  , .DI       (GND_BUS_16[15:0])
  , .DWE      (GND_BIT         )
  , .PSCLK    (ps_cntrl_clk    )
  , .PSEN     (ps_en           )
  , .PSINCDEC (ps_inc_dec      )
  , .RST      (reset_cmt)
  , .CLKDV    (                )
  , .CLKFX    (rx_dcm_clk224   )
  , .CLKFX180 (                )
  , .CLK0     (rx_dcm_clk32    )
  , .CLK2X    (                )
  , .CLK2X180 (                )
  , .CLK90    (                ) 
  , .CLK180   (                )
  , .CLK270   (                )
  , .DO       (                )
  , .DRDY     (                )
  , .LOCKED   (dcm_locked      )
  , .PSDONE   (ps_done         )
  ) ;

 

 

Tags (4)
dcm_initial.jpg
dcm_pscmd_128.jpg
dcm_pscmd_255.jpg
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1 Reply
Highlighted
Scholar
Scholar
9,003 Views
Registered: ‎02-27-2008

p,

 

I seem to recall that the models do not support the actual phase shift, they only accurately reflect the handshake of the control signals.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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