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Registered: ‎03-29-2009

V5 LV50T FIFO bit errors

I have a design that write to a FIFO in a 166MHZ clock domain and read in a 332MHz clock domain.  The clock domain are unrelated.  I have a TIG constraint between these two clock domains.  I am getting bit errors reading out of the FIFO.  I am using first word fall through with the valid flag.  I have tried implementing this FIFO using the FIFO generator using distributed RAM and block RAM.  Both implementations show this problem.  The timing report shows now errors.


I have other asynchronous FIFOs running at slower rates that don't show this problem.  Is there a possible vulnerability in the way I am using it?


I am in the process of trying it with the built in FIFO structure.


I appreciate any insights you have.

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