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Visitor mbryk
Visitor
11,520 Views
Registered: ‎05-29-2013

V5 LVCMOS drive currents

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Hi,

 

I have a Virtex-5 which had 21 I/O each connected through 47 ohm resistors configured for LVCMOS33, slow slew rate, 12mA default drive current to the inputs of multiple chips that were running off of a power rail that had hit its current-limit causing the rail to foldback and produce ~2.2V rail voltage on the chips (the FPGA VCCO was running off of a different voltage).  I also had one additional I/O connected to an input on the same rail that had no series resistor.  I believe the Virtex-5 I/O, which were switching on and off, were powering these chips.  The V5 VCCO rail was very close to 3.3V, so given a 0.3V ESD diode drop on the chips being powered through their I/O, I calculate that the 21 I/O could have had a 0.8V drop across the 47 ohm resistor drawing roughly 17mA per I/O and 357mA total, with the I/O line without a series resistor drawing an unknown amount of current.  Now I know that this much current didnt flow through because the power draw into my board never exceeded a value such that these I/O could be drawing more than about 105mA.  As a side note the FPGA ESD diodes almost certainly never came into play and were not forward-biased.

Looking at the V5 datasheet (DS202) there is the "Total current applied to an I/O pin, powered or unpowered" of 100mA which is very high, and looks like I'd be in the clear (assuming a drive strength of 12mA MEANS it wont exceed much beyond 12mA when shorted).  However, there;s the subsequent constraint that "Total current applied to all I/O pins, powered or unpowered" is also 100mA.  Given the above situation, its conceivable that the other I/O that was using simultaneously could have drawn more than 20mA, causing me to exceed this maximum output current constraint of all the I/O on the FPGA. 

 

It was connected like this for approximately 5 minutes. 

 

 

My questions are:
1. Is the maximum current in or out of any pin constraint relaxed when the current is coming out of the pin being provided by the FPGA?

2. is there any sort of I-V curve for the output behavoir of an I/O pin configured for a 12mA drive strength to determine what the likely voltage-drop was across my 47 ohm resistors was and therefore their output current, and what the current out of the pin that was not connected through any resistor?

3. amd did my above situation cause any damage to the FPGA that could mainfest itself as a failure of the later down the line?

 

Thanks,

Max

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1 Solution

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Scholar austin
Scholar
19,300 Views
Registered: ‎02-27-2008

Re: V5 LVCMOS drive currents

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Max,

 

1. Is the maximum current in or out of any pin constraint relaxed when the current is coming out of the pin being provided by the FPGA?

 

If you look at the IBIS model you will see the actual current.  The 12 mA default is the minimum guaranteed, at the Vil, or Vih points.  The actual current is much more, in order to meet the min spec.

 

2. is there any sort of I-V curve for the output behavoir of an I/O pin configured for a 12mA drive strength to determine what the likely voltage-drop was across my 47 ohm resistors was and therefore their output current, and what the current out of the pin that was not connected through any resistor?

 

Run the IBIS models in a simulator to answer all questions.

 

3. and did my above situation cause any damage to the FPGA that could mainfest itself as a failure of the later down the line?

 

No, no damage resulted from any of this, as it never exceeded the absolute maximum specifications (see datasheet to confirm, as I have to guess the junction temperature was not exceeded, etc.).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

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4 Replies
Scholar austin
Scholar
19,301 Views
Registered: ‎02-27-2008

Re: V5 LVCMOS drive currents

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Max,

 

1. Is the maximum current in or out of any pin constraint relaxed when the current is coming out of the pin being provided by the FPGA?

 

If you look at the IBIS model you will see the actual current.  The 12 mA default is the minimum guaranteed, at the Vil, or Vih points.  The actual current is much more, in order to meet the min spec.

 

2. is there any sort of I-V curve for the output behavoir of an I/O pin configured for a 12mA drive strength to determine what the likely voltage-drop was across my 47 ohm resistors was and therefore their output current, and what the current out of the pin that was not connected through any resistor?

 

Run the IBIS models in a simulator to answer all questions.

 

3. and did my above situation cause any damage to the FPGA that could mainfest itself as a failure of the later down the line?

 

No, no damage resulted from any of this, as it never exceeded the absolute maximum specifications (see datasheet to confirm, as I have to guess the junction temperature was not exceeded, etc.).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

View solution in original post

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Visitor mbryk
Visitor
11,507 Views
Registered: ‎05-29-2013

Re: V5 LVCMOS drive currents

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Hi Austin,

 

What about the maximum rating "Total current applied to all I/O pins, powered or unpowered" which is +/-100mA?  if the total output power from all my I/O that were connected in this way were drawing a sum total of >105mA, wouldn't this maximum rating be violated?

 

Thanks,

Max

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Scholar austin
Scholar
11,504 Views
Registered: ‎02-27-2008

Re: V5 LVCMOS drive currents

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Yes, and no,

 

That specification is to prevent IO latchup (reverse bias of protection structures which are themselves pnpn devices, intrinsic to the device).


If no latchup was observed (you would know, instantly), then it did  not happen (you got lucky, or as for your part, more current than that was required, in a reverse bias way through the substrate body diodes).

 

So, no latch-up, no harm.

 

By the by, latch up usually ends in the part melting a hole, or catching fire.  The fact that we work hard to prevent this by proper design and specification means that latch up of IO's is extremely rare, and only happens when a system is designed wrong AND other bad things happen to overstress the IO.  I have never seen a latch up of a Xilinx device, nor have I heard of one.  I have seen charred remains from lightning strikes.  Was that a latch up?  Who cares!  It was a lightning bolt!

 

 

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
Visitor mbryk
Visitor
11,494 Views
Registered: ‎05-29-2013

Re: V5 LVCMOS drive currents

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Haha, lightning from part of a test? or just some very interesting circumstances?

 

Thanks so much for the quick response!

 

Regards,

Max

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