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Visitor
Visitor
7,784 Views
Registered: ‎02-12-2016

VHDL programming with Vertex6 series X6-1000M

Hi,

 

Can anyone help me in implementing some simple VHDL program(I was trying conditional pulsing) on Vertex6 series X6-1000M, what I am looking for is how to properly map pins and other constrains to get output on the DACs. I also tried reading pin constrains from programs compiled using simulink but every time it uses different pins for input to DACs. It would be great if someone can sahre a working program written directly in VHDL/Verilog(and not compiled through simulink).

 

 

Thanks,

Arpit.

 

PS: We have been using simuling for programming the FPGA and I am trying to get started with basic VHDL programming on Vertex6 series X6-1000M and having really hard time trying to figure out the pin constrains. I went through the manuals, pin maps and what not, but did not find what I was looking for. I did search through the forum for the same but no luck(if I missed something please point me in the right direction).

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Highlighted
Scholar
Scholar
7,768 Views
Registered: ‎02-27-2008

a,

 

The universal constraints file format (.ucf files) may be used to specify where the pins/signals/names will appear.

 

Check the board support package (demonstration designs) for Virtex 6 boards:

 

http://www.xilinx.com/products/boards-and-kits/ek-v6-ml605-g.html

 

(under documentaion and designs -- download the examples, and look at them).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Visitor
Visitor
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Registered: ‎02-12-2016

Thanks for your reply Austin. I am familiar with basics of programming FPGA using VHDL. For example if I want to get clock input from pin A1 I can do that by adding "NET CLK_P LOC = A1". The part that I am struggling with is pin maps, figuring out which pin corresponds to what. For that I went through Pin Map for this board(LX240T) available at http://www.xilinx.com/support/documentation/user_guides/ug365.pdf but could not get anything useful. I am stuck and any help would be appreciated.


Arpit.

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Visitor
Visitor
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Registered: ‎02-12-2016

With some tries and pulling pin maps from Simulink generated constraints files, I was able to control the LEDs on the board, but still no luck with getting any output on DACs. I am posting VHDL code and constraints file that I used, please let me know if you have any idea why this might not be working.

 

Thanks,

Arpit.

 

----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;


entity main is
    Port ( sys_clk_p : in STD_Logic;
              sys_clk_n : in STD_Logic;
           dac0_data_p: out  STD_LOGIC_VECTOR (15 downto 0);
              dac0_data_n: out  STD_LOGIC_VECTOR (15 downto 0);
              dac0_clk_in_p : out STD_Logic;
              dac0_clk_in_n : out STD_Logic;
              LED : out  STD_LOGIC_VECTOR (2 downto 0)
              );
end main;

architecture Behavioral of main is

signal count : STD_Logic_Vector (15 downto 0) := (others=>'0');
signal DAC0 : STD_Logic_Vector (15 downto 0) := (others=>'0');
--signal outzr : STD_Logic_Vector (15 downto 0) := (others=>'0');
signal sys_clk : STD_Logic :='0';
signal LEDs : STD_Logic_Vector (2 downto 0) := (others=>'0');
signal mil125 : STD_Logic_Vector (27 downto 0) := (others=>'0');
--signal mil125 : STD_Logic_Vector (26 downto 0) := (others=>'0');


begin

       IBUFGDS_inst : IBUFGDS
   generic map (
      DIFF_TERM => FALSE, -- Differential Termination
      IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
      IOSTANDARD => "DIFF_SSTL18_I")
   port map (
      O => sys_clk,  -- Clock buffer output
      I => sys_clk_p,  -- Diff_p clock buffer input (connect directly to top-level port)
      IB => sys_clk_n -- Diff_n clock buffer input (connect directly to top-level port)
   );
   
    OBUFDS_inst : OBUFDS
   generic map (
      IOSTANDARD => "LVDS_25")
   port map (
      O => dac0_clk_in_p,     -- Diff_p output (connect directly to top-level port)
      OB => dac0_clk_in_n,   -- Diff_n output (connect directly to top-level port)
      I => sys_clk      -- Buffer input
   );
   
    OBUFDS_loop : for i in 0 to 15 generate
        OBUFDS_inst : OBUFDS
        generic map (
            IOSTANDARD => "LVDS_25")
        port map (
            O => dac0_data_p(i),    -- Diff_p output (connect directly to top-level port)
            OB => dac0_data_n(i),   -- Diff_n output (connect directly to top-level port)
            I => DAC0(i)      -- Buffer input
        );
    end generate;
   
    LEDPing: process(sys_clk)
    begin
        if rising_edge(sys_clk) then
            count <= count+1;
            if mil125 < "1011111010111100001000000000" then mil125 <= mil125 + 1;
            else mil125 <= (others=>'0'); LEDs <= LEDs+1;
            end if;
        end if;
    end process;
   
    DAC0 <= count;
    LED <= LEDs;

end Behavioral;

-----------------------------------------------------------------------------------

 

Constraints File :

 


############################################################################

NET sys_clk_p      LOC = K24 | IOSTANDARD = DIFF_SSTL18_I;  #Bank 24
NET sys_clk_n      LOC = K23 | IOSTANDARD = DIFF_SSTL18_I;  #Bank 24


############################################################################

# DAC interface (data) constraints
NET dac?_clk_in_?  IOSTANDARD = LVDS_25;
NET dac?_data_?[*] IOSTANDARD = LVDS_25;



# DAC0 interface
NET dac0_clk_in_p   LOC = N33;  #Bank 15
NET dac0_clk_in_n   LOC = M33;  #Bank 15
NET dac0_data_p[0]  LOC = N34;  #Bank 15
NET dac0_data_n[0]  LOC = P34;  #Bank 15
NET dac0_data_p[1]  LOC = N32;  #Bank 15
NET dac0_data_n[1]  LOC = P32;  #Bank 15
NET dac0_data_p[2]  LOC = R31;  #Bank 15
NET dac0_data_n[2]  LOC = R32;  #Bank 15
NET dac0_data_p[3]  LOC = P31;  #Bank 15
NET dac0_data_n[3]  LOC = P30;  #Bank 15
NET dac0_data_p[4]  LOC = L33;  #Bank 15
NET dac0_data_n[4]  LOC = M32;  #Bank 15
NET dac0_data_p[5]  LOC = P25;  #Bank 15
NET dac0_data_n[5]  LOC = P26;  #Bank 15
NET dac0_data_p[6]  LOC = N27;  #Bank 15
NET dac0_data_n[6]  LOC = P27;  #Bank 15
NET dac0_data_p[7]  LOC = M30;  #Bank 15
NET dac0_data_n[7]  LOC = N30;  #Bank 15
NET dac0_data_p[8]  LOC = L28;  #Bank 15
NET dac0_data_n[8]  LOC = M28;  #Bank 15
NET dac0_data_p[9]  LOC = L29;  #Bank 15
NET dac0_data_n[9]  LOC = L30;  #Bank 15
NET dac0_data_p[10] LOC = M31;  #Bank 15
NET dac0_data_n[10] LOC = L31;  #Bank 15
NET dac0_data_p[11] LOC = F31;  #Bank 16
NET dac0_data_n[11] LOC = E31;  #Bank 16
NET dac0_data_p[12] LOC = E34;  #Bank 16
NET dac0_data_n[12] LOC = F34;  #Bank 16
NET dac0_data_p[13] LOC = D31;  #Bank 16
NET dac0_data_n[13] LOC = D32;  #Bank 16
NET dac0_data_p[14] LOC = G32;  #Bank 16
NET dac0_data_n[14] LOC = H32;  #Bank 16
NET dac0_data_p[15] LOC = J30;  #Bank 16
NET dac0_data_n[15] LOC = K29;  #Bank 16


# LED
NET led[*]           IOSTANDARD = LVCMOS25;
NET led[0]           LOC = D34;  #Bank 16
NET led[1]           LOC = J26;  #Bank 16
NET led[2]           LOC = J27;  #Bank 16

 


############################################################################

 

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